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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AT89LP51 датащи(PDF) 43 Page - ATMEL Corporation |
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AT89LP51 датащи(HTML) 43 Page - ATMEL Corporation |
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43 / 113 page  43 3709C–MICRO–5/11 AT89LP51/52 - Preliminary Figure 10-1. Quasi-bidirectional Output Figure 10-2. Input Only Figure 10-3. Input Circuit for P3.2, P3.3, P4.6 and P4.7 10.1.3 Open-drain Output The open-drain output configuration turns off all pull-ups and only drives the pull-down transistor of the port pin when the port latch contains a logic “0”. To be used as a logic output, a port con- figured in this manner must have an external pull-up, typically a resistor tied to V DD. The pull- down for this mode is the same as for the quasi-bidirectional mode. The open-drain port configu- ration is shown in Figure 10-4. The input circuitry of P3.2, P3.3, P4.6 and P4.7 is not disabled during Power-down (see Figure 10-3) and therefore these pins should not be left floating during Power-down when configured in this mode. Figure 10-4. Open-Drain Output 1 Clock Delay (D Flip-Flop) Strong Very Weak Weak Port Pin VCC VCC VCC From Port Register Input Data PWD Port Pin Input Data PWD Port Pin Input Data Port Pin From Port Register Input Data PWD |
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