ACT5830 datasheet(24/41 Pages) ACTIVE-SEMI

24 / 41 page

LOW-DROPOUT LINEAR REGULATORS

ACT5830

Rev 2, 20-Jan-11

Innovative Power

- 24 -

www.active-semi.com

ActivePMU

TM is a trademark of Active-Semi.

2CTM is a trademark of NXP.

FUNCTIONAL DESCRIPTIONS

General Description

The ACT5830 features eight high performance, low-

dropout, low-noise and low quiescent current LDOs

with high PSRR.

Programming Output Voltages (VSET)

All LDOs feature independently-programmable

output voltages that are set via the I2C serial

interface, increasing the ACT5830 flexibility while

reducing total solution size and cost.

Set

the

output

voltage

writing

the

LDOx/VSET[_]

See

Table

LDO1234568/VSET[4:0]

and

Table

LDO7/VSET[_] Output Voltage Settings for a

detailed

description

voltage

programming

options.

Enabling and Disabling LDOs

For information regarding enabling and disabling

the LDOs during the startup and shutdown

sequence section. Once the startup routine is

completed

the

remaining

LDOs

can

enabled/disabled via either the I2C interface or the

TCXO_EN

(LDO4),

RX_EN

(LDO5),

TX_EN

(LDO6), and PWR_HOLD (LDO1, LDO2, LDO3,

LDO7, and LDO8).

Reference Bypass Pin

The ACT5830 contains a conference bypass pin

which filters noise from the reference, providing a

low-noise voltage reference to the LDOs. Bypass

REF to G with a 0.01µF ceramic capacitor.

Compensation and Stability

The LDOs need an output capacitor for stability.

This capacitor should be connected directly

between the output and G pin, as close to the

output as possible, and with a short, direct

connection to maximize device’s performance. To

ensure best performance for the device, the output

capacitor should have a minimum capacitance of

1µF, and ESR value between 10mΩ and 500mΩ.

High quality ceramic capacitors such as X7R and

X5R dielectric types are strongly recommended.

See the Capacitor Selection section for more

information.

Capacitor Selection

The input capacitor reduces peak currents and

noise at the voltage source. Connect a low ESR

bulk capacitor (>1μF suggested) to the input. Select

this bulk capacitor to meet the input ripple

requirements and voltage rating, rather than

capacitor size.

PCB Layout Considerations

The ACT5830’s LDOs provide good DC, AC, and

noise performance over a wide range of operating

conditions, and are relatively insensitive to layout

considerations. When designing a PCB, however,

careful layout is necessary to prevent other circuitry

from degrading LDO performance.

A good design places input and output capacitors

as close to the LDO inputs and output as possible,

and utilizes a star-ground configuration for all

regulators

prevent

noise-coupling

through

ground. Output traces should be routed to avoid

close proximity to noisy nodes, particularly the SW

nodes of the DC/DC.

REF is a filtered reference noise, and internally has

a direct connection to the linear regulator controller.

Any noise injected onto REF will directly affect the

outputs of the linear regulators, and therefore

special care should be taken to ensure that no

noise is injected to the outputs via REF. As with the

LDO output capacitors, the REF by pass capacitor

should be placed as close to the IC as possible,

with short, direct connections to the star-ground.

Avoid the use of vias whenever possible. Noisy

nodes, such as from the DC/DC, should be routed

as far away from REF as possible.

ACT5830 датащи(PDF) 24 Page - Active-Semi, Inc

ACT5830 датащи(HTML) 24 Page - Active-Semi, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41

датащи скачать

ссылки URL