LH28F008SA datasheet(2/27 Pages) SHARP

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LH28F008SA

8M (1M × 8) Flash Memory

28F008SA-16

TOP VIEW

A11

A10

A13

A14

A16

A18

A12

A15

44-PIN SOP

RY/BY

DQ7

DQ6

DQ5

DQ2

DQ3

DQ1

DQ0

GND

VCC

A17

A19

VPP

DQ4

VCC

Figure 2. 44-Pin SOP Configuration

INTRODUCTION

SHARP’S LH28F008SA 8M Flash File™ Memory is

the highest density nonvolatile read/write solution for

solid state storage. The LH28F008SA’s extended

cycling, symmetrically blocked architecture, fast access

time, write automation and low power consumption pro-

vide a more reliable, lower power, lighter weight and

higher performance alternative to traditional rotating disk

technology. The LH28F008SA brings new capabilities

to portable computing. Application and operating sys-

tem software stored in resident flash memory arrays

provide instant-on rapid execute-in-place and protec-

tion from obsolescence through in-system software

updates. Resident software also extends system bat-

tery life and increases relaibility by reducing disk drive

accesses.

For high density data acquisition applications, the

LH28F008SA offers a more cost-effective and reliable

alternative to SRAM and battery. Traditional high

density embedded applications, such as telecommuni-

cations, can take advantage of the LH28F008SA’s

nonvolatility, blocking and minimal system code require-

ments for flexible firmware and modular software

designs.

The LH28F008SA is offered in 40-pin TSOP (stan-

dard) package. Pin assignments simplify board layout

when integrating multiple devices in a flash memory

array or subsystem. This device uses an integrated

Command User Interface and state machine for simpli-

fied block erasure and byte write. The LH28F008SA

memory map consists of 16 separately erasable

64K blocks.

SHARP’s LH28F008SA employs advanced CMOS

circuitry for systems requiring low power consumption

and noise immunity. Its 85 ns access time provides

superior performance when compared with magnetic

storage media. A deep powerdown mode lowers power

consumption to 1 µW typical throughVCC, crucial in por-

table computing, handheld instrumentation and other

low-power applications. The PWD power control input

also provides absolute data protection during system

power up/down.

DESCRIPTION

The LH28F008SA is a high-perfor mance 8M

(8,388,608 bit) memory organized at 1M (1,048,576

bytes) of 8 bits each. Sixteen 64K (65,536 Byte) blocks

are included on the LH28F008SA. A memory map is

shown in Figure 4 of this specification. A block erase

operation erases one of the sixteen blocks of memory

in typically 1.6 seconds, independent of the remaining

blocks. Each block can be independently erased and

written 100,000 cyles. Erase Suspend mode allows sys-

tem software to suspend block erase to read data or

execute code from any other block of the LH28F008SA.

The LH28F008SA is available in the 40-pin TSOP

(Thin Small Outline Package, 1.2 mm thick) package.

Pinouts are shown in Figure 1 of this specification.

The Command User Interface serves as the inter-

face between the microprocessor or microcontroller and

the internal operation of the LH28F008SA.

Byte Write and Block Erase Automation allow byte

write and block erase operations to be executed using

a two-write command sequence to the Command User

Interface. The internal Write State Machine (WSM)

automatically executes the algorithms and timings nec-

essary for byte write and block erase operations,

including verifications, thereby unburdening the micro-

processor or microcontroller. Writing of memory data is

performed in byte increments typically within 9 µs, an

80% improvement over current flash memory products.

IPP byte write and block erase currents are 10 mA typi-

cal, 30 mA maximum. VPP byte write and block erase

voltage is 11.4 V to 12.5 V.

The Status Register indicates the status of the WSM

and when the WSM successfully completes the desired

byte write or block erase operation.

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