DAC3482 datasheet(7/79 Pages) TI1

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DAC3482

www.ti.com

SLAS748A

– MARCH 2011 – REVISED JUNE 2011

ELECTRICAL CHARACTERISTICS

– DC SPECIFICATIONS

(1)

over recommended operating free-air temperature range, nominal supplies, IOUTFS = 20mA (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Resolution

Bits

DC ACCURACY

DNL

Differential nonlinearity

±2

LSB

1 LSB = IOUTFS/2

INL

Integral nonlinearity

±4

LSB

ANALOG OUTPUT

Coarse gain linearity

±0.04

LSB

Offset error

Mid code offset

±0.001

%FSR

Gain error

With external reference

±2

%FSR

With internal reference

±2

%FSR

Gain mismatch

With internal reference

±2

%FSR

Full scale output current

Output compliance range

–0.5

0.6

Output resistance

300

Output capacitance

REFERENCE OUTPUT

VREF

Reference output voltage

1.2

Reference output current(2)

100

REFERENCE INPUT

VEXTIO

Input voltage range

0.6

1.2

1.25

External Reference Mode

Input resistance

Small signal bandwidth

472

kHz

Input capacitance

100

TEMPERATURE COEFFICIENTS

Offset drift

±1

ppm/

°C

With external reference

±15

ppm/

°C

Gain drift

With internal reference

±30

ppm/

°C

Reference voltage drift

±8

ppm/

°C

POWER SUPPLY

AVDD, IOVDD, PLLAVDD

3.14

3.3

3.46

CLKVDD, DACVDD, DIGVDD

1.14

1.2

1.26

PSRR

Power supply rejection ratio

DC tested

±0.2

%FSR/V

POWER CONSUMPTION

I(AVDD)

Analog supply current(3)

MODE 1

I(DIGVDD)

Digital supply current

390

450

fDAC = 1.25GSPS, 2x interpolation, Mixer on,

I(DACVDD)

DAC supply current

QMC on, invsinc on,

I(CLKVDD)

Clock supply current

110

PLL enabled, 20mA FS output, IF = 200MHz

Power dissipation

882

980

I(AVDD)

Analog supply current(3)

MODE 2

I(DIGVDD)

Digital supply current

385

fDAC = 1.25GSPS, 2x interpolation, Mixer on,

I(DACVDD)

DAC supply current

QMC on, invsinc on,

I(CLKVDD)

Clock supply current

PLL disabled, 20mA FS output, IF = 200MHz

Power dissipation

800

(1)

Measured differentially across IOUTP/N with 25

Ω each to GND.

(2)

Use an external buffer amplifier with high impedance input to drive any external load.

(3)

Includes AVDD, PLLAVDD, and IOVDD

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