DAC3482 datasheet(49/79 Pages) TI1

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Clock Generator

DATACLKP/N

FRAMEP/N

FPGA

D[15:0]P/N

DATACLKP/N

FRAMEP/N

DACCLKP/N

B0454-01

LVPECL Outputs

OSTRP/N

LVPECL Outputs

DACCLKP/N

OSTRP/N

PLL/

DLL

DAC3482 DAC1

Delay 1

Delay 2

Outputs are

Phase Aligned

DAC3482 DAC2

Variable delays due to variations in the FPGA(s) output

paths or board level wiring or temperature/voltage deltas

T0526-01

DACCLKP/N(2)

DACCLKP/N(1)

•

OSTRP/N(2)

OSTRP/N(1)

S(OSTR)

SKEW ~ 0

H(OSTR)

DAC3482

www.ti.com

SLAS748A

– MARCH 2011 – REVISED JUNE 2011

Figure 57. Synchronization System in Dual Sync Sources Mode with PLL Bypassed

For correct operation both OSTR and DACCLK must be generated from the same clock domain. The OSTR

signal is sampled by DACCLK and must satisfy the timing requirements in the specifications table. If the clock

generator does not have the ability to delay the DACCLK to meet the OSTR timing requirement, the polarity of

the DACCLK outputs can be swapped with respect to the OSTR ones to create 180 degree phase delay of the

DACCLK. This may help establish proper setup and hold time requirement of the OSTR signal.

Careful board layout planning must be done to ensure that the DACCLK and OSTR signals are distributed from

device to device with the lowest skew possible as this will affect the synchronization process. In order to

minimize the skew across devices it is recommended to use the same clock distribution device to provide the

DACCLK and OSTR signals to all the DAC devices in the system.

Figure 58. Timing Diagram for LVPECL Synchronization Signals

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