MPC8548E datasheet(89/143 Pages) FREESCALE

89 / 143 page

MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 8

Freescale Semiconductor

Package Description

Notes:

1. All d

imensions are in millimeters.

2. Dimensioning and tolerancing per ASME Y14.5M-1994.

3. Maximum solder ball diameter measured parallel to datum A.

4. Datum A, the seating plane, is determined by the spherical crowns of the solder balls.

5. Parallelism measurement shall exclude any effect of mark on top surface of package.

6. All dimensions are symmetric across the package center lines unless dimensioned otherwise.

19.3

Pinout Listings

NOTE

The DMA_DACK[0:1] and TEST_SEL/TEST_SEL pins must be set to a

proper state during POR configuration. Refer to the pinlist table of the

individual device for more details.

For MPC8548/47/45, GPIOs are still available on

PCI1_AD[63:32]/PC2_AD[31:0] pins if they are not used for PCI

functionality.

For MPC8545/43, eTSEC does not support 16 bit FIFO mode.

Table 71 provides the pinout listing for the MPC8548E 783 FC-PBGA package.

Table 71. MPC8548E Pinout Listing

Signal

Package Pin Number

Pin Type

Power

Supply

Notes

PCI1 and PCI2 (One 64-Bit or Two 32-Bit)

PCI1_AD[63:32]/PCI2_AD[31:0]

AB14, AC15, AA15, Y16, W16, AB16, AC16,

AA16, AE17, AA18, W18, AC17, AD16, AE16,

Y17, AC18, AB18, AA19, AB19, AB21, AA20,

AC20, AB20, AB22, AC22, AD21, AB23, AF23,

AD23, AE23, AC23, AC24

I/O

OVDD

PCI1_AD[31:0]

AH6, AE7, AF7, AG7, AH7, AF8, AH8, AE9,

AH9, AC10, AB10, AD10, AG10, AA10, AH10,

AA11, AB12, AE12, AG12, AH12, AB13, AA12,

AC13, AE13, Y14, W13, AG13, V14, AH13,

AC14, Y15, AB15

I/O

OVDD

PCI1_C_BE[7:4]/PCI2_C_BE[3:0]

AF15, AD14, AE15, AD15

I/O

OVDD

PCI1_C_BE[3:0]

AF9, AD11, Y12, Y13

I/O

OVDD

PCI1_PAR64/PCI2_PAR

W15

I/O

OVDD

PCI1_GNT[4:1]

AG6, AE6, AF5, AH5

OVDD

5, 9, 35

PCI1_GNT0

AG5

I/O

OVDD

—

PCI1_IRDY

AF11

I/O

OVDD

PCI1_PAR

AD12

I/O

OVDD

—

PCI1_PERR

AC12

I/O

OVDD

PCI1_SERR

V13

I/O

OVDD

2, 4

PCI1_STOP

W12

I/O

OVDD

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