MPC8548E datasheet(68/143 Pages) FREESCALE

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MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 8

Freescale Semiconductor

High-Speed Serial Interfaces (HSSI)

Figure 46 shows the SerDes reference clock connection reference circuits for a single-ended clock driver.

It assumes the DC levels of the clock driver are compatible with the MPC8548E SerDes reference clock

input’s DC requirement.

Figure 46. Single-Ended Connection (Reference Only)

16.2.4

AC Requirements for SerDes Reference Clocks

The clock driver selected should provide a high quality reference clock with low phase noise and

cycle-to-cycle jitter. Phase noise less than 100 kHz can be tracked by the PLL and data recovery loops and

is less of a problem. Phase noise above 15 MHz is filtered by the PLL. The most problematic phase noise

occurs in the 1–15 MHz range. The source impedance of the clock driver should be 50

Ω to match the

transmission line and reduce reflections which are a source of noise to the system.

The detailed AC requirements of the SerDes reference clocks is defined by each interface protocol based

on application usage. Refer to the following sections for detailed information:

•

Section 17.2, “AC Requirements for PCI Express SerDes Clocks”

•

Section 18.2, “AC Requirements for Serial RapidIO SD_REF_CLK and SD_REF_CLK”

16.2.4.1

Spread Spectrum Clock

SD_REF_CLK/SD_REF_CLK are designed to work with a spread spectrum clock (+0% to –0.5%

spreading at 30–33 kHz rate is allowed), assuming both ends have same reference clock. For better results,

a source without significant unintended modulation should be used.

SD_REF_CLK

100

Ω Differential PWB Trace

Clock Driver

CLK_Out

Single-Ended CLK

Driver Chip

MPC8548E

Total 50

Ω. Assume clock driver’s

output impedance is about 16

Ω.

SerDes Refer.

CLK Receiver

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