MPC8548E datasheet(65/143 Pages) FREESCALE

номер детали	MPC8548E

подробное описание детали	PowerQUICC III Integrated Processor Hardware Specifications

PDF	143 Pages

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производитель	FREESCALE [Freescale Semiconductor, Inc]

домашняя страница	http://www.freescale.com

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MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 8

Freescale Semiconductor

High-Speed Serial Interfaces (HSSI)

or AC-coupled into the unused phase (SD_REF_CLK) through the same source impedance as

the clock input (SD_REF_CLK) in use.

Figure 40. Differential Reference Clock Input DC Requirements (External DC-Coupled)

Figure 41. Differential Reference Clock Input DC Requirements (External AC-Coupled)

Figure 42. Single-Ended Reference Clock Input DC Requirements

16.2.3

Interfacing with Other Differential Signaling Levels

•

With on-chip termination to SGND_SRDSn (xcorevss), the differential reference clocks inputs are

HCSL (high-speed current steering logic) compatible DC-coupled.

•

Many other low voltage differential type outputs like LVDS (low voltage differential signaling) can

be used but may need to be AC-coupled due to the limited common mode input range allowed (100

to 400 mV) for DC-coupled connection.

•

LVPECL outputs can produce signal with too large amplitude and may need to be DC-biased at

clock driver output first, then followed with series attenuation resistor to reduce the amplitude, in

addition to AC-coupling.

SD_REF_CLK

Vmax < 800 mV

Vmin > 0V

100 mV < Vcm < 400 mV

200 mV < Input Amplitude or Differential Peak < 800 mV

SD_REF_CLK

Vcm

200 mV < Input Amplitude or Differential Peak < 800 mV

Vmax < Vcm + 400 mV

Vmin > Vcm – 400 mV

SD_REF_CLK

400 mV < SD_REF_CLK Input Amplitude < 800 mV

0 V

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