LTC4263 datasheet(12/28 Pages) LINER

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LTC4274

4274fa

PIN FUNCTIONS

RESET: Chip Reset, Active Low. When the RESET pin is

low, the LTC4274 is held inactive with all ports off and all

internal registers reset to their power-up states. When

RESETispulledhigh,theLTC4274beginsnormaloperation.

RESET can be connected to an external capacitor or RC

network to provide a power turn-on delay. Internal filter-

ing of the RESET pin prevents glitches less than 1μs wide

from resetting the LTC4274. Internally pulled up to VDD.

MID: Midspan Mode Input. When high, the LTC4274 acts

as a midspan device. Internally pulled down to DGND.

INT: Interrupt Output, Open Drain. INT will pull low when

any one of several events occur in the LTC4274. It will

return to a high impedance state when bits 6 or 7 are set

in the Reset PB register (1Ah). The INT signal can be used

to generate an interrupt to the host processor, eliminating

the need for continuous software polling. Individual INT

events can be disabled using the Int Mask register (01h).

See the LTC4274 Software Programming documentation

for more information. The INT pin is only updated between

I2C transactions.

SCL: Serial Clock Input. High impedance clock input for

the I2C serial interface bus. SCL must be tied high if not

used.

SDAOUT: Serial Data Output, Open Drain Data Output for

the I2C Serial Interface Bus. The LTC4274 uses two pins

to implement the bidirectional SDA function to simplify

optoisolation of the I2C bus. To implement a standard

bidirectional SDA pin, tie SDAOUT and SDAIN together.

SDAOUT should be grounded or left floating if not used.

See Applications Information for more information.

SDAIN: Serial Data Input. High impedance data input for

the I2C serial interface bus. The LTC4274 uses two pins

to implement the bidirectional SDA function to simplify

optoisolation of the I2C bus. To implement a standard

bidirectional SDA pin, tie SDAOUT and SDAIN together.

SDAIN must be tied high if not used. See Applications

Information for more information.

AD3: Address Bit 3. Tie the address pins high or low to set

the I2C serial address to which the LTC4274 responds. This

address will be 010A3A2A1A0b. Internally pulled up to VDD.

AD2: Address Bit 2. See AD3.

AD1: Address Bit 1. See AD3.

AD0: Address Bit 0. See AD3.

NC, DNC: All pins identified with “NC” or “DNC” must be

left unconnected.

DGND: Digital Ground. DGND is the return for the VDD

supply.

VDD: Logic Power Supply. Connect to a 3.3V power supply

relative to DGND. VDD must be bypassed to DGND near

the LTC4274 with at least a 0.1μF capacitor.

SHDN: Shutdown, Active Low. When pulled low, SHDN

shuts down the port, regardless of the state of the internal

registers. Pulling SHDN low is equivalent to setting the

Reset Port bit in the Reset Pushbutton register (1Ah).

Internal filtering of the SHDN pin prevents glitches less

than 1μs wide from reseting the port. Internally pulled

up to VDD.

AGND: Analog Ground. AGND is the return for the VEE

supply.

SENSE: Current Sense Input. SENSE monitors the exter-

nal MOSFET current via a 0.5Ω or 0.25Ω sense resistor

between SENSE and VEE. Whenever the voltage across

the sense resistor exceeds the overcurrent detection

threshold VCUT, the current limit fault timer counts up. If

the voltage across the sense resistor reaches the current

limit threshold VLIM, the GATE pin voltage is lowered to

maintain constant current in the external MOSFET. See

Applications Information for further details.

GATE: Gate Drive. GATE should be connected to the gate

of the external MOSFET for the port. When the MOSFET

is turned on, the gate voltage is driven to 13V (typ) above

VEE. During a current limit condition, the voltage at GATE

will be reduced to maintain constant current through the

external MOSFET. If the fault timer expires, GATE is pulled

down, turning the MOSFET off and recording a tCUT or

tSTART event.

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