Analog Integrated Circuit Device Data

Freescale Semiconductor

33

33981

ADDITIONAL DOCUMENTATION

THERMAL ADDENDUM (REV 2.0)

ADDITIONAL DOCUMENTATION

THERMAL ADDENDUM (REV 2.0)

INTRODUCTION

This thermal addendum is provided as a supplement to the 33981 technical

datasheet. The addendum provides thermal performance information that may be

critical in the design and development of system applications. All electrical,

application, and packaging information is provided in the datasheet.

PACKAGING AND THERMAL CONSIDERATIONS

This package is a dual die package. There are two heat sources in the package

For m, n = 1, R

For m = 1, n = 2, R

R

The stated values are solely for a thermal performance comparison of one package to another in a standardized environment.

This methodology is not meant to and will not predict the performance of a package in an application-specific environment. Stated

values were obtained by measurement and simulation according to the standards listed below.

STANDARDS

Figure 44. Surface mount for power PQFN

with exposed pads

16-PIN

PQFN

33981

PNA SUFFIX

98ARL10521D

16-PIN PQFN

12 MM X 12 MM

Note For package dimensions, refer to

the 33981 device datasheet.

=

.

Table 7. Thermal Performance Comparison

Thermal

Resistance

1 = Power Chip, 2 = Logic Chip [

°C/W]

m = 1,

n = 1

m = 1, n = 2

m = 2, n = 1

m = 2,

n = 2

(1), (2)

22

18

41

(2), (3)

7.0

4.0

27

(1), (4)

62

48

81

(5)

<1.0

0.0

1.0

Notes

1.

Per JEDEC JESD51-2 at natural convection, still air

condition.

2.

2s2p thermal test board per JEDEC JESD51-7and

JESD51-5.

3.

Per JEDEC JESD51-8, with the board temperature on the

center trace near the power outputs.

4.

Single layer thermal test board per JEDEC JESD51-3 and

JESD51-5.

5.

Thermal resistance between the die junction and the

exposed pad, “infinite” heat sink attached to exposed pad.

0.2 mm spacing

between PCB pads

Note: Recommended via diameter is 0.5 mm. PTH (plated through

hole) via must be plugged / filled with epoxy or solder mask in order

to minimize void formation and to avoid any solder wicking into the

via.

0.2 mm spacing

between PCB pads