33910 datasheet(83/90 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

33910

FUNCTIONAL DEVICE OPERATIONS

LOGIC COMMANDS AND REGISTERS

MC33910BAC / MC34910BAC

CYSTx - Cyclic Sense Period Prescaler Select

This write-only bits selects the interval for the wake-up

cyclic sensing together with the bit CYSX8 in the

configuration register (CFR) (see Configuration Register -

CFR).

This option is only active if the high side switch is enabled

when entering in Stop or Sleep mode. Otherwise a timed

wake-up is performed after the period shown in Table 51.

Table 51. Cyclic Sense Interval

Watchdog Status Register

This register returns the watchdog status information and

is also returned when writing to the TIMCR.

WDTO - Watchdog Time Out

This read-only bit signals the last reset was caused by

either a watchdog timeout or by an attempt to clear the

watchdog within the window closed.

Any access to this register or the TIMCR will clear the

WDTO bit.

1 = Last reset caused by watchdog timeout

0 = None

WDERR - Watchdog Error

This read-only bit signals the detection of a missing

watchdog resistor. In this condition the watchdog is using the

internal, lower precision timebase. The windowing function is

disabled.

1 = WDCONF pin resistor missing

0 = WDCONF pin resistor not floating

WDOFF - Watchdog Off

This read-only bit signals that the watchdog pin connected

to GND and therefore disabled. In this case watchdog

timeouts are disabled and the device automatically enters

Normal mode out of Reset. This might be necessary for

software debugging and for programming the Flash memory.

1 = Watchdog is disabled

0 = Watchdog is enabled

WDWO - Watchdog Window Open

This read-only bit signals when the watchdog window is

open for clears. The purpose of this bit is for testing. Should

be ignored in case WDERR is High.

1 = Watchdog window open

0 = Watchdog window closed

Analog Multiplexer Control Register - MUXCR

This register controls the analog multiplexer and selects

the divider ration for the L1 input divider.

L1DS - L1 Analog Input Divider Select

This write-only bit selects the resistor divider for the L1

analog input. Voltage is internally clamped to VDD.

0 = L1 Analog divider: 1

1 = L1 Analog divider: 3.6 (typ.)

CYSX8(123) CYST2

CYST1

CYST0

Interval

No Cyclic Sense

20 ms

40 ms

60 ms

80 ms

100 ms

120 ms

140 ms

160 ms

320 ms

480 ms

640 ms

800 ms

960 ms

1120 ms

Notes

123.

bit CYSX8 is located in configuration register (CFR)

Table 52. Watchdog Status Register - $A/$B

Read

WDTO

WDERR

WDOFF

WDWO

Table 53. Analog Multiplexer Control Register -$C

Write

L1DS

MX2

MX1

MX0

Reset Value

Reset Condition

POR

POR, Reset mode or ext_reset

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