33910 datasheet(82/90 Pages) FREESCALE

82 / 90 page

Analog Integrated Circuit Device Data

Freescale Semiconductor

33910

FUNCTIONAL DEVICE OPERATIONS

LOGIC COMMANDS AND REGISTERS

MC33910BAC / MC34910BAC

High Side Control Register - HSCR

This register controls the operation of the high side drivers.

Writing to this register returns the High Side Status Register

(HSSR).

PWMHSx - PWM Input Control Enable

This write-only bit enables/disables the PWMIN input pin

to control the high side switch. The high side switch must be

enabled (HSx bit).

1 = PWMIN input controls HS1 output.

0 = HSx is controlled only by SPI.

HSx - High Side Switch Control.

This write-only bit enables/disables the high side switch.

1 = HSx switch on.

0 = HSx switch off.

High Side Status Register - HSSR

This register returns the status of the high side switch and

is also returned when writing to the HSCR.

High Side thermal shutdown

A thermal shutdown of the high side drivers is indicated by

setting the HSxOP and HSxCL bits simultaneously.

HSxOP - High Side Switch Open-Load Detection

This read-only bit signals that the high side switch is

conducting current below a certain threshold indicating

possible load disconnection.

1 = HSx Open Load detected (or thermal shutdown)

0 = Normal

HSxCL - High Side Current Limitation

This read-only bit indicates that the high side switch is

operating in current Limitation mode.

1 = HSx in current limitation (or thermal shutdown)

0 = Normal

Timing Control Register - TIMCR

This register is a double purpose register which allows to

configure the watchdog and the cyclic sense periods. Writing

to the TIMCR will also return the WDSR.

CS/WD - Cyclic Sense or Watchdog Prescaler Select.

This write-only bit selects which prescaler is being written

to, the cyclic sense prescaler or the watchdog prescaler.

1 = Cyclic Sense Prescaler selected

0 = Watchdog Prescaler select

WDx - Watchdog Prescaler

This write-only bits selects the divider for the watchdog

prescaler and therefore selects the watchdog period in

accordance with Table 50. This configuration is valid only if

windowing watchdog is active.

Table 50. Watchdog Prescaler

Table 47. High Side Control Register - $6

Write

PWMHS2

PWMHS1

HS2

HS1

Reset

Value

Reset

Condition

POR

POR, Reset mode, ext_reset, HSx

over-temp or (VSOV & HVSE)

Table 48. High Side Status Register - $6/$7

Read

HS2OP

HS2CL

HS1OP

HS1CL

Table 49. Timing Control Register - $A

Write

CS/WD

WD2

WD1

WD0

CYST2

CYST1

CYST0

Reset

Value

000

Reset

Condition

-POR

WD2

WD1

WD0

Prescaler Divider

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