33480 datasheet(16/39 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

33480

FUNCTIONAL DESCRIPTION

INTRODUCTION

FUNCTIONAL DESCRIPTION

INTRODUCTION

The 33480 is designed for low-voltage automotive and

industrial lighting applications. Its five low RDS(ON) MOSFETs

(three 10 m

Ω and two 35 mΩ) can control the high sides of

five separate resistive loads (bulbs). Programming, control,

and diagnostics are accomplished using a 16-bit SPI

interface.

FUNCTIONAL TERMINAL DESCRIPTION

SUPPLY VOLTAGE (VBAT)

The VBAT terminal of the 33480 is the power supply of the

device. In addition to its supply function, this tab contributes

to the thermal behavior of the device by conducting the heat

from the switching MOSFETs to the printed circuit board.

SUPPLY VOLTAGE (VCC)

This is an external voltage input terminal used to supply

the SPI digital portion of the circuit and the gate driver of the

external SMART MOSFET.

GROUND (GND)

This terminal is the ground of the device.

CLOCK INPUT (CLOCK)

The PWM frequency and timing are generated from clock

input by the PWM module. The clock input frequency is the

factor 27 = 128 of the PWM frequency (60 Hz to 240 Hz). The

OUT1:6 can be controlled in the range of 4% to 96% with a

resolution of 7 bits of duty cycle (bits D[6:0]).

The following table describes the PWM resolution.

The timing includes four programmable PWM switching

phases (0°, 90°, 180°, and 270°) to improve overall EMC

behavior of the light module.

The amplitude of the input current is divided by four while

the frequency is 4 times the original one. The two following

pictures illustrate this behavior.

The synchronization of the switching phases between

different corner light IC is provided by an SPI command in

combination with the CS input. The bit in the SPI is called

PWM sync (initialization register).

In Normal Mode, no PWM feature (100% duty cycle) is

provided in the following instances:

• with the following SPI configuration: D7:D0=FF.

• In case of clock input signal failure (out of fPWM), the

outputs state depends of D7 bit value (D7=1=ON) in

Normal Mode.

In Fail mode. The ouputs state depends of IGN and

Flasher terminals.

LIMP HOME INPUT (LIMP)

The Fail mode of the component can be activated by this

digital input port. The signal is “high active”, meaning the Fail

mode can be activated by a logic high signal at the input.

On/Off

(Bit D7)

Duty cycle (7 bits

resolution)

Output state

OFF

0000000

PWM (1/128 duty cycle)

0000001

PWM (2/128 duty cycle)

0000010

PWM (3/128 duty cycle)

1111111

fully ON

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