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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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33480 датащи(PDF) 28 Page - Freescale Semiconductor, Inc |
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33480 датащи(HTML) 28 Page - Freescale Semiconductor, Inc |
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28 / 39 page  Analog Integrated Circuit Device Data 28 Freescale Semiconductor 33480 FUNCTIONAL DESCRIPTION PROTECTION AND DIAGNOSIS FEATURES FUNCTIONAL DESCRIPTION SERIAL INPUT COMMUNICATION SPI communication is accomplished using 16-bit messages. A message is transmitted by the master starting with the MSB, D15, and ending with the LSB, D0. Each incoming command message on the SI terminal can be interpreted using the bit assignment described in Table 7. The 5 bits D15:D11, called register address bits, are used to select the command register. Bit D10 is the watchdog bit. The remaining 10 bits, D9:D0, are used to configure and control the output and its protection features. Multiple messages can be transmitted in succession to accommodate those applications where daisy chaining is desirable or to confirm transmitted data as long as the messages are all multiples of 16 bits. Any attempt made to latch in a message that is not 16 bits will be ignored. All SPI registers are reset (all bit equal 0) in case of RSTB equal 0 or fail mode (Fail=1). DEVICE REGISTER ADDRESSING The register addresses (D15:D11) and the impact of the serial input registers on device operation are described in this section. Table 8 summarizes the SI registers. Note: testmode address used only by FSL is D[15:11]=01111 with RSTB voltage higher than 8V typ. ADDRESS 00000—INITIALIZATION The Initialization register is used to read the various statuses, choose one of the six outputs current recopy, load the H7 bulbs profile for OUT2 only, and synchronize the switching phases between different corner light devices. The register bits D1 and D0 determine the content of the 16 bits of the next SO data. (Refer to the section entitled Serial Output Communication (Device Status Return Data) beginning on page 30.) Table 9 describes the register of initialization. Table 7. SI Message Bit Assignment Bit Sig SI Msg Bit Message Bit Description MSB D15:D11 Register address bits. D10 Watchdog in: toggled to satisfy watchdog requirements. LSB D9:D0 Used to configure inputs, outputs, device protection features, and SO status content. Table 8. Serial Input Address and Configuration Bit Map SI Register SI Address SI Data D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Initialization 0 0 0 0 0 WD 0 0 0 PWM sync Xenon MUX2 MUX1 MUX0 SOA1 SOA0 Config OL 0 0 0 0 1 WD 0 0 0 0 0 OLLED5 OLLED4 OLLED3 OLLED2 OLLED1 Unused 0 0 0 1 0 WD 0 0 0 0 0 0 0 0 0 0 Unused 0 0 0 1 1 WD 0 0 0 0 0 0 0 0 0 0 Control OUT1 0 1 0 0 1 WD Phase2 Phase1 ONoff PWM6 PWM5 PWM4 PWM3 PWM2 PWM1 PWM0 Control OUT2 0 1 0 1 0 WD Phase2 Phase1 ONoff PWM6 PWM5 PWM4 PWM3 PWM2 PWM1 PWM0 Control OUT3 0 1 0 1 1 WD Phase2 Phase1 ONoff PWM6 PWM5 PWM4 PWM3 PWM2 PWM1 PWM0 Control OUT4 0 1 1 0 0 WD Phase2 Phase1 ONoff PWM6 PWM5 PWM4 PWM3 PWM2 PWM1 PWM0 Control OUT5 0 1 1 0 1 WD Phase2 Phase1 ONoff PWM6 PWM5 PWM4 PWM3 PWM2 PWM1 PWM0 Control External Switch 0 1 1 1 0 WD Phase2 Phase1 ONoff PWM6 PWM5 PWM4 PWM3 PWM2 PWM1 PWM0 RESET X X X X X 0 0 0 0 0 0 0 0 0 0 0 |
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