MPC8544E datasheet(39/117 Pages) FREESCALE

39 / 117 page

MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

Enhanced Three-Speed Ethernet (eTSEC), MII Management

Figure 22 shows the RGMII and RTBI AC timing and multiplexing diagrams.

Figure 22. RGMII and RTBI AC Timing and Multiplexing Diagrams

Fall time (20%–80%)

tRGTF

—

0.75

—

Notes:

1. In general, the clock reference symbol representation for this section is based on the symbols RGT to represent RGMII and

RTBI timing. For example, the subscript of tRGT represents the TBI (T) receive (RX) clock. Note also that the notation for rise

(R) and fall (F) times follows the clock symbol that is being represented. For symbols representing skews, the subscript is

skew (SK) followed by the clock that is being skewed (RGT).

2. This implies that PC board design will require clocks to be routed such that an additional trace delay of greater than 1.5 ns

will be added to the associated clock signal.

3. For 10 and 100 Mbps, tRGT scales to 400 ns ± 40 ns and 40 ns ± 4 ns, respectively.

4. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as long

as the minimum duty cycle is not violated and stretching occurs for no more than three tRGT of the lowest speed transitioned

between.

5. Guaranteed by design.

Table 37. RGMII and RTBI AC Timing Specifications (continued)

At recommended operating conditions with L/TVDD of 2.5 V ± 5%.

Parameter/Condition

Symbol1

Min

Typ

Max

Unit

Notes

GTX_CLK

tRGT

tRGTH

tSKRGT_TX

TX_CTL

TXD[8:5]

TXD[7:4]

TXD[9]

TXERR

TXD[4]

TXEN

TXD[3:0]

(At Transmitter)

TXD[8:5][3:0]

TXD[7:4][3:0]

TX_CLK

(At PHY)

RX_CTL

RXD[8:5]

RXD[7:4]

RXD[9]

RXERR

RXD[4]

RXDV

RXD[3:0]

RX_CLK

(At PHY)

tSKRGT_RX

tSKRGT_TX

tRGTH

tRGT

GTX_CLK

(At Receiver)

RXD[8:5][3:0]

RXD[7:4][3:0]

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