Evaluation Kit User Manual for FX828 and FX829

EV8000

© 2004 CML Microsystems Plc

29

UM8000/4

1.6.3.24 FX829 Bit Error Rate Testing

To allow the user to perform FX829 Bit Error Rate Testing (BERT) the EF8000 firmware contains

a BERT routine, configured by the ES8000 Windows Application software. This facility requires

two EV8000 signalling processor boards (near and far) and user input to both near and far FX829

device forms before BERT can commence.

Hardware Setup

This function enables connection to a BER Testers as follows:

µC Board J2 Pin 1 to Tester Tx Data O/P

µC Board J2 Pin 2 to Tester Tx Clock I/P

µC Board J2 Pin 3 to Tester Rx Data I/P

µC Board J2 Pin 4 to Tester Rx Clock I/P

The Tester must be able to operate from an external clock. The timings of the clocks provided

from the µC board are as follows:

1 Byte Time

1 Byte Time

Tx Clock

Rx Clock

t

A

t

B

Data is assumed to be clocked in and out of the Tester on the rising edge of either Rx or Tx clock.

The FX829 FFSK data from the transmitting signalling processor board can be directly fed from

FFSK/DTMF Out (J6 Pin 15) into noise summing circuitry, or via one of the FX829 modulator

paths. The output of the noise summing stage should be connected into DEMODIN (J6 Pin 21) of

the receiving signalling processor board.

Application Software Setup

After executing the ES8000 Windows Application software the user should open the near and far

FX829 device forms. Select FFSKTX, TXIDLEM and TXDATAM on the device form used to

control the transmit end. Other write register bits may need to be enabled if the user is not

transmitting directly from FFSK/DTMF Out (J6 Pin 15). On the device form used to control the

receive end, select FFSKRX, AMP1 and one of the required synchronisation primes.

When the near and far FX829 device forms have been configured select the BER Test command

from the Global pulldown menu. The BER Test pop-up window will now appear with a read-only

edit box providing status information on the BER Test.