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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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MPC8533E датащи(PDF) 89 Page - Freescale Semiconductor, Inc |
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MPC8533E датащи(HTML) 89 Page - Freescale Semiconductor, Inc |
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89 / 112 page  MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor 89 Clocking Note that there is no default for this PLL ratio; these signals must be pulled to the desired values. Also note that the DDR data rate is the determining factor in selecting the CCB bus frequency, since the CCB frequency must equal the DDR data rate. 19.3 e500 Core PLL Ratio Table 61 describes the clock ratio between the e500 core complex bus (CCB) and the e500 core clock. This ratio is determined by the binary value of LBCTL, LALE, and LGPL2 at power up, as shown in Table 61. 19.4 PCI Clocks For specifications on the PCI_CLK, refer to the PCI 2.2 Local Bus Specifications. The use of PCI_CLK is optional if SYSCLK is in the range of 33–66 MHz. If SYSCLK is outside this range then use of PCI_CLK is required as a separate PCI clock source, asynchronous with respect to SYSCLK. Table 60. CCB Clock Ratio Binary Value of LA[28:31] Signals CCB:SYSCLK Ratio Binary Value of LA[28:31] Signals CCB:SYSCLK Ratio 0000 16:1 1000 8:1 0001 Reserved 1001 9:1 0010 Reserved 1010 10:1 0011 3:1 1011 Reserved 0100 4:1 1100 12:1 0101 5:1 1101 Reserved 0110 6:1 1110 Reserved 0111 Reserved 1111 Reserved Table 61. e500 Core to CCB Clock Ratio Binary Value of LBCTL, LALE, LGPL2 Signals e500 core:CCB Clock Ratio Binary Value of LBCTL, LALE, LGPL2 Signals e500 core:CCB Clock Ratio 000 4:1 100 2:1 001 Reserved 101 5:2 010 Reserved 110 3:1 011 3:2 111 7:2 |
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