MPC8533E datasheet(60/112 Pages) FREESCALE

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MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

High-Speed Serial Interfaces (HSSI)

Figure 40. Differential Voltage Definitions for Transmitter or Receiver

To illustrate these definitions using real values, consider the case of a CML (Current Mode Logic)

transmitter that has a common mode voltage of 2.25 V and each of its outputs, TD and TD, has a swing

that goes between 2.5 V and 2.0 V. Using these values, the peak-to-peak voltage swing of each signal (TD

or TD) is 500 mV p-p, which is referred as the single-ended swing for each signal. In this example, since

the differential signaling environment is fully symmetrical, the transmitter output’s differential swing

(VOD) has the same amplitude as each signal’s single-ended swing. The differential output signal ranges

between 500 mV and –500 mV, in other words, VOD is 500 mV in one phase and –500 mV in the other

phase. The peak differential voltage (VDIFFp) is 500 mV. The peak-to-peak differential voltage (VDIFFp-p)

is 1000 mV p-p.

16.2

SerDes Reference Clocks

The SerDes reference clock inputs are applied to an internal PLL whose output creates the clock used by

the corresponding SerDes lanes. The SerDes reference clocks inputs are SD1_REF_CLK and

SD1_REF_CLK for PCI Express1 PCI Express2. SD2_REF_CLK and SD2_REF_CLK for the PCI

Express3. The following sections describe the SerDes reference clock requirements and some application

information.

16.2.1

SerDes Reference Clock Receiver Characteristics

Figure 41 shows a receiver reference diagram of the SerDes reference clocks.

•

The supply voltage requirements for XVDD_SRDS2 are specified in Table 1 and Table 2.

•

SerDes reference clock receiver reference circuit structure

— The SDn_REF_CLK and SDn_REF_CLK are internally AC-coupled differential inputs as

shown in Figure 41. Each differential clock input (SDn_REF_CLK or SDn_REF_CLK) has a

50-

Ω termination to SGND_SRDSn (xcorevss) followed by on-chip AC-coupling.

— The external reference clock driver must be able to drive this termination.

Differential Swing, VID or VOD = A – B

A Volts

B Volts

SDn_TX or

SDn_RX

SDn_TX or

SDn_RX

Differential Peak Voltage, VDIFFp = |A – B|

Differential Peak-Peak Voltage, VDIFFpp = 2*VDIFFp (not shown)

Vcm = (A + B) / 2

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