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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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MPC8533E датащи(PDF) 26 Page - Freescale Semiconductor, Inc |
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MPC8533E датащи(HTML) 26 Page - Freescale Semiconductor, Inc |
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26 / 112 page  MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4 26 Freescale Semiconductor Enhanced Three-Speed Ethernet (eTSEC), MII Management Timing diagrams for FIFO appear in Figure 7 and Figure 8. Figure 7. FIFO Transmit AC Timing Diagram Figure 8. FIFO Receive AC Timing Diagram 8.3.2 GMII AC Timing Specifications This section describes the GMII transmit and receive AC timing specifications. 8.3.2.1 GMII Transmit AC Timing Specifications Table 25 provides the GMII transmit AC timing specifications. Rise time RX_CLK (20%–80%) tFIRR — — 0.75 ns — Fall time RX_CLK (80%–20%) tFIRF — — 0.75 ns — RXD[7:0], RX_DV, RX_ER setup time to RX_CLK tFIRDV 1.5 — — ns — RX_CLK to RXD[7:0], RX_DV, RX_ER hold time tFIRDX 0.5 — — ns — Table 25. GMII Transmit AC Timing Specifications At recommended operating conditions with L/TVDD of 3.3 V ± 5% or 2.5 V ± 5% Parameter/Condition Symbol1 Min Typ Max Unit Notes GTX_CLK clock period tGTX — 8.0 —ns— GTX_CLK to GMII data TXD[7:0], TX_ER, TX_EN delay tGTKHDX 0.2 — 5.0 ns 2 GTX_CLK data clock rise time (20%-80%) tGTXR —— 1.0 ns Table 24. FIFO Mode Receive AC Timing Specification (continued) At recommended operating conditions with L/TVDD of 3.3 V ± 5% or 2.5 V ± 5% Parameter/Condition Symbol Min Typ Max Unit Notes tFITF TXD[7:0] TX_EN GTX_CLK TX_ER tFITDV tFITR tFITH tFIT tFITDX tFIRF tFIRR RX_CLK RXD[7:0] RX_DV RX_ER Valid Data tFIRDX tFIRDV tFIRH tFIR |
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