PCA85232DA datasheet(7/54 Pages) NXP

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PCA85232

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Product data sheet

Rev. 1 — 8 December 2010

7 of 54

NXP Semiconductors

PCA85232

LCD driver for low multiplex rates

The host microprocessor or microcontroller maintains the 2-line I2C-bus communication

channel with the PCA85232.

Biasing voltages for the multiplexed LCD waveforms are generated internally, removing

the need for an external bias generator. The internal oscillator is selected by connecting

pin OSC to VSS. The only other connections required to complete the system are the

power supplies (VDD, VSS,and VLCD) and the LCD panel selected for the application.

7.1 Power-On Reset (POR)

At power-on the PCA85232 resets to the following starting conditions:

• All backplane and segment outputs are set to VLCD

• The selected drive mode is 1:4 multiplex with 1⁄3 bias

• Blinking is switched off

• Input and output bank selectors are reset

• The I2C-bus interface is initialized

• The data pointer and the subaddress counter are cleared (set to logic 0)

• The display is disabled

• If internal oscillator is selected (pin OSC connected to VSS), then there is no clock

signal on pin CLK

Remark: Do not transfer data on the I2C-bus for at least 1 ms after a power-on to allow

the reset action to complete.

7.2 LCD bias generator

Fractional LCD biasing voltages are obtained from an internal voltage divider consisting of

three impedances connected in series between VLCD and VSS. The center impedance is

bypassed by switch if the 1

⁄

2 bias voltage level for the 1:2 multiplex drive mode

configuration is selected.

Fig 4.

Typical system configuration

HOST

MICRO-

PROCESSOR/

MICRO-

CONTROLLER

≤

2CB

SDA

SDAACK

SCL

OSC

160 segment drives

4 backplanes

LCD PANEL

(up to 640

elements)

PCA85232

SA0

VDD

VSS

VDD

VLCD

013aaa284

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