IR3876MBF datasheet(12/20 Pages) IRF

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IR3876MBF

CIRCUIT DESCRIPTION

STABILITY CONSIDERATIONS

Constant-on-time control is a fast , ripple based

control scheme. Unstable operation can occur

if certain conditions are not met. The system

instability is usually caused by:

• Switching noise coupled to FB input. This

causes the PWM comparator to trigger

prematurely after the 400ns minimum Q2 on-

time. It will result in double or multiple pulses

every switching cycle instead of the expected

single pulse. Double pulsing can causes

higher output voltage ripple, but in most

application it will not affect operation. This can

usually be prevented by careful layout of the

ground plane and the FB sensing trace.

• Steady state ripple on FB pin being too small.

The PWM comparator in IR3876 requires

minimum 7mVp-p ripple voltage to operate

stably. Not enough ripple will result in similar

double pulsing issue described above. Solving

this may require using output capacitors with

higher ESR. Another way to solve this is to

add a ~10pF ceramic capacitor from Vout to

FB to couple more Vout ripple to the FB pin.

• ESR loop instability. The stability criteria of

constant on-time is: ESR*Cout>Ton/2. If ESR

is too small that this criteria is violated then

sub-harmonic oscillation will occur. This is

similar to the instability problem of peak-

current-mode control with D>0.5. Increasing

ESR is the most effective way to stabilize the

system, but the price paid is the larger output

voltage ripple.

• For applications with all ceramic output

capacitors, the ESR is usually too small to

meet

the

stability

criteria.

these

applications, external slope compensation is

necessary to make the loop stable. The ramp

injection circuit, composed of R6, C13, and

C14, shown in Figure 7 is required. The

inductor current ripple sensed by R6 and C13

is AC coupled to the FB pin through C14. The

injected ramp slope can be adjusted by

changing the RC time constant of R6 and

C13, which is similar to the circuit used for

DCR current sensing. C14 is typically chosen

by C14

(R7//R8)=Ton.

OVER CURRENT MONITOR

The over current circuitry monitors the output

current during each switching cycle. The voltage

across the synchronous MOSFET, VPHASE, is

monitored for over current and zero crossing. The

minimum LGATE interval allows time to sample

VPHASE.

The over current trip point is programmed with a

resistor from the ISET pin to PHASE pin, as

shown in equation 3, where Tj is the junction

temperature of Q2 at operation conditions, and 0.4

is the temperature coefficient (~4000 ppm/

C) of

Q2 Rdson. When over current is detected, the

output gates are tri-state and SS voltage is pulled

to 0V. This initiates a new soft start cycle. If there

was a total of three OC events, the IR3876 will

disable switching. Toggling VCC or EN will allow

the next start up.

OVER VOLTAGE PROTECTION

The IR3876 monitors the voltage at the FB node.

If the FB voltage is above the over voltage

threshold, the gates are turned off and the

PGOOD signal is pulled low. Toggling VCC will

allow the next start up.

(3)

0.4)

100

DSON

SET

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