IR3876MBF datasheet(11/20 Pages) IRF

11 / 20 page

IR3876MBF

GATE DRIVE LOGIC

The gate drive logic features adaptive dead

time, diode emulation, and a minimum lower

gate interval.

adaptive

dead

time

prevents

the

simultaneous conduction of the upper and lower

MOSFETs. The lower gate voltage (LGATE)

must be below approximately 1V after PWM

goes HIGH before the upper MOSFET can be

gated on. Also, the upper gate voltage

(UGATE), the difference voltage between

UGATE

and

PHASE,

must

below

approximately 1V after PWM goes LOW before

the lower MOSFET can be gated on.

The control MOSFET is gated on after the

adaptive delay for PWM = HIGH and the

synchronous MOSFET is gated on after the

adaptive delay for PWM = LOW. The lower

MOSFET is driven ‘off’ when the signal

ZCROSS indicates that the inductor current has

reversed as detected by the PHASE voltage

crossing the zero current threshold. The

synchronous MOSFET stays ‘off’ until the next

PWM falling edge. When the lower peak of

inductor current is above zero, a forced

continuous current condition is selected. The

control MOSFET is gated on after the adaptive

delay for PWM = HIGH, and the synchronous

MOSFET is gated on after the adaptive delay for

PWM = LOW.

The synchronous MOSFET gate is driven on for

a minimum duration. This minimum duration

allows time to recharge the bootstrap capacitor

and allows the current monitor to sample the

PHASE voltage.

PWM COMPARATOR

The PWM comparator initiates a SET signal

(PWM pulse) when the FB pin falls below the

reference (VREF) or the soft start (SS) voltage.

ON-TIME GENERATOR

The PWM on-time duration is programmed with

an external resistor (RFF) from the input supply

(VIN) to the FF pin. The simplified equation for

RFF is shown in equation 1. The FF pin is held to

an internal reference after EN goes HIGH. A copy

of the current in RFF charges a timing capacitor,

which sets the on-time duration, as shown in

equation 2.

SOFT START

An internal 10µA current source charges the

external capacitor on the SS pin to set the output

voltage slew rate during the soft start interval. The

output voltage reaches regulation when the FB pin

is above the under voltage threshold and the UV#

= HIGH. Once the voltage on the SS pin is above

the PGOOD delay threshold, the combination of

the SSDelay and UV# signals release the

PGOOD pin. With EN = LOW, the capacitor

voltage and SS pin is held to the FB pin voltage.

CIRCUIT DESCRIPTION

(2)





(1)

OUT





CONTROL LOGIC

The control logic monitors input power sources,

sequences the converter through the soft-start

and protective modes, and indicates output

voltage status on the PGOOD pin.

VCC and

3VCBP pins are continuously monitored, and the

IR3876 will be disabled if the voltage of either pin

drops below the falling thresholds.

The IR3876 will initiate a soft start when VCC is in

the normal range and the EN pin = HIGH. In the

event of a sustained overload, a counter keeps

track of four soft-start cycles and then disables the

IR3876. The overload counter is only reset by EN

or UVLO.

IR3876MBF датащи(PDF) 11 Page - International Rectifier

IR3876MBF датащи(HTML) 11 Page - International Rectifier

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

датащи скачать

ссылки URL