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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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STM32F101X8 датащи(PDF) 68 Page - STMicroelectronics |
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STM32F101X8 датащи(HTML) 68 Page - STMicroelectronics |
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68 / 85 page  Electrical characteristics STM32F101x8, STM32F101xB 68/85 Doc ID 13586 Rev 13 Figure 34. Typical connection diagram using the ADC 1. Refer to Table 41 for the values of RAIN, RADC and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy this, fADC should be reduced. General PCB design guidelines Power supply decoupling should be performed as shown in Figure 35 or Figure 36, depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip. Figure 35. Power supply and reference decoupling (VREF+ not connected to VDDA) 1. VREF+ and VREF- inputs are available only on 100-pin packages. ai14139d STM32F10xxx VDD AINx IL±1 µA 0.6 V VT RAIN(1) Cparasitic VAIN 0.6 V VT RADC(1) CADC(1) 12-bit converter Sample and hold ADC converter V REF+ STM32F10xxx V DDA V SSA/V REF- 1 µF // 10 nF 1 µF // 10 nF ai14380b |
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