M48T37Y datasheet(17/30 Pages) STMICROELECTRONICS

17 / 30 page

M48T37Y, M48T37V

Clock operations

Doc ID 7019 Rev 9

17/30

The watchdog timer is disabled by writing a value of 00000000 to the eight bits in the

watchdog register. Should the watchdog timer time out, a value of 00h needs to be written to

the watchdog register in order to clear the IRQ/FT pin.

The watchdog function is automatically disabled upon power-down and the watchdog

frequency test function is activated, the watchdog or alarm function prevails and the

frequency test function is denied. The WDI pin should be connected to VSS if not used.

3.7

Power-on reset

The M48T37Y/V continuously monitors VCC. When VCC falls to the power fail detect trip

point, the RST pulls low (open drain) and remains low on power-up for tREC after VCC

passes VPFD. RST is valid for all VCC conditions. The RST pin is an open drain output and

an appropriate resistor to VCC should be chosen to control rise time (see Figure 13 on

page 22).

3.8

Programmable interrupts

The M48T37Y/V provides two programmable interrupts: an alarm and a watchdog. When an

interrupt condition occurs, the M48T37Y/V sets the appropriate flag bit in the flag register

7FF0h. The interrupt enable bits (AFE and ABE) in 7FF6h and the watchdog steering

(WDS) bit in 7FF7h allow the interrupt to activate the IRQ/FT pin.

The alarm flag and the IRQ/FT output are cleared by a READ to the flags register. An

interrupt condition reset will not occur unless the addresses are stable at the flag location for

at least 15 ns while the device is in the READ mode as shown in Figure 7 on page 14.

The IRQ/FT pin is an open drain output and requires a pull-up resistor (10 k

recommended) to VCC. The pin remains in the high impedance state unless an interrupt

occurs or the frequency test mode is enabled.

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