Clock operations

M48T37Y, M48T37V

12/30

Doc ID 7019 Rev 9

3

Clock operations

3.1

Reading the clock

prevent reading data in transition. The BiPORT™ TIMEKEEPER cells in the RAM array are

only data registers and not the actual clock counters, so updating the registers can be halted

without disturbing the clock itself.

Updating is halted when a '1' is written to the READ bit, D6 in the control register 7FF8h. As

long as a '1' remains in that position, updating is halted. After a halt is issued, the registers

reflect the count; that is, the day, date, and the time that were current at the moment the halt

command was issued.

All of the TIMEKEEPER registers are updated simultaneously. A halt will not interrupt an

update in progress. Updating will resume within a second after the bit is reset to a '0.'

3.2

Setting the clock

Bit D7 of the control register (7FF8h) is the WRITE bit. Setting the WRITE bit to a '1,' like the

READ bit, halts updates to the TIMEKEEPER registers. The user can then load them with

the correct day, date, and time data in 24-hour BCD format (see Table 5 on page 13).

Resetting the WRITE bit to a '0' then transfers the values of all time registers (7FF1h,

7FF9h-7FFFh) to the actual TIMEKEEPER counters and allows normal operation to

resume. After the WRITE bit is reset, the next clock update will occur in approximately one

second.

Note:

Upon power-up following a power failure, both the WRITE bit and the READ bit will be reset

to '0.'

3.3

Stopping and starting the oscillator

The oscillator may be stopped at any time. If the device is going to spend a significant

amount of time on the shelf, the oscillator can be turned off to minimize current drain on the

battery. The STOP bit is the MSB of the seconds register. Setting it to a '1' stops the

oscillator. When reset to a '0,' the M48T37Y/V oscillator starts within one second.

Note:

It is not necessary to set the WRITE bit when setting or resetting the FREQUENCY TEST

bit (FT) or the STOP bit (ST).