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WLCSP16 датащи(PDF) 22 Page - NXP Semiconductors |
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WLCSP16 датащи(HTML) 22 Page - NXP Semiconductors |
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22 / 38 page ![]() LPC1102 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Objective data sheet Rev. 00 — 23 June 2010 22 of 38 NXP Semiconductors LPC1102 32-bit ARM Cortex-M0 microcontroller Conditions: Tamb = 25 °C; active mode entered executing code while(1){} from flash; all peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL= 0x1F); all peripheral clocks disabled; internal pull-up resistors disabled; BOD disabled. (1) System PLL disabled; IRC enabled. (2) System PLL enabled; IRC disabled. Fig 6. Active mode: Typical supply current IDD versus supply voltage VDD for different system clock frequencies Conditions: VDD = 3.3 V; active mode entered executing code while(1){} from flash; all peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL= 0x1F); all peripheral clocks disabled; internal pull-up resistors disabled; BOD disabled. (1) System PLL disabled; IRC enabled. (2) System PLL enabled; IRC disabled. Fig 7. Active mode: Typical supply current IDD versus temperature for different system clock frequencies X (X) X X X XX 001aac984 X X X X X X (X) X <tbd> X (X) X X X XX 001aac984 X X X X X X (X) X <tbd> |
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