AT25DF641A datasheet(48/57 Pages) ATMEL

48 / 57 page

8693A–DFLASH–8/10

Atmel AT25DF641A [Preliminary]

Notes:

1. Not 100% tested (value guaranteed by design and characterization)

2. 15pF load at frequencies above 70MHz, 30pF otherwise

3. Only applicable as a constraint for the Write Status Register Byte 1 command when SPRL = 1

14.5

AC Characteristics – All Other Parameters

Symbol

Parameter

Min

Max

Units

CLKH

Clock High Time

4.3

CLKL

Clock Low Time

4.3

CLKR

(1)

Clock Rise Time, Peak-to-Peak (Slew Rate)

0.1

V/ns

CLKF

(1)

Clock Fall Time, Peak-to-Peak (Slew Rate)

0.1

V/ns

CSH

Chip Select High Time

CSLS

Chip Select Low Setup Time (relative to Clock)

CSLH

Chip Select Low Hold Time (relative to Clock)

CSHS

Chip Select High Setup Time (relative to Clock)

CSHH

Chip Select High Hold Time (relative to Clock)

Data In Setup Time

2ns

Data In Hold Time

1ns

DIS

(1)

Output Disable Time

5ns

(2)

Output Valid Time

5ns

Output Hold Time

2ns

HLS

HOLD Low Setup Time (relative to Clock)

HLH

HOLD Low Hold Time (relative to Clock)

HHS

HOLD High Setup Time (relative to Clock)

HHH

HOLD High Hold Time (relative to Clock)

HLQZ

(1)

HOLD Low to Output High-Z

5ns

HHQX

(1)

HOLD High to Output Low-Z

5ns

WPS

(1)(3)

Write Protect Setup Time

WPH

(1)(3)

Write Protect Hold Time

100

SECP

(1)

Sector Protect Time (from Chip Select High)

SECUP

(1)

Sector Unprotect Time (from Chip Select High)

LOCK

(1)

Sector Lockdown and Freeze Sector Lockdown State Time (from Chip Select High)

200

µs

EDPD

(1)

Chip Select High to Deep Power-Down

µs

RDPD

(1)

Chip Select High to Standby Mode

µs

RST

Reset Time

µs

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