AT25DF641A datasheet(45/57 Pages) ATMEL

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8693A–DFLASH–8/10

Atmel AT25DF641A [Preliminary]

To end the Hold mode and resume serial communication, the HOLD pin must be deasserted

during the SCK low pulse. If the HOLD pin is deasserted during the SCK high pulse, then the

Hold mode won’t end until the beginning of the next SCK low pulse.

If the CS pin is deasserted while the HOLD pin is still asserted, then any operation that may

have been started will be aborted, and the device will reset the WEL bit in the Status Register

back to the logical “0” state.

Figure 12-5. Hold Mode

13. Atmel RapidS Implementation

To implement Atmel® RapidS™ and operate at clock frequencies higher than what can be

achieved in a viable SPI implementation, a full clock cycle can be used to transmit data back and

forth across the serial bus. The Atmel AT25DF641A is designed to always clock its data out on

the falling edge of the SCK signal and clock data in on the rising edge of SCK.

For full clock cycle operation to be achieved, when the AT25DF641A is clocking data out on the

falling edge of SCK, the host controller should wait until the next falling edge of SCK to latch the

data in. Similarly, the host controller should clock its data out on the rising edge of SCK in order

to give the AT25DF641A a full clock cycle to latch the incoming data in on the next rising edge of

SCK.

Implementing RapidS allows a system to run at higher clock frequencies since a full clock cycle

is used to accommodate a device’s clock-to-output time, input setup time, and associated

rise/fall times. For example, if the system clock frequency is 100MHz (10ns cycle time) with a

50% duty cycle, and the host controller has an input setup time of 2ns, then a standard SPI

implementation would require that the slave device be capable of outputting its data in less than

3ns to meet the 2ns host controller setup time [(10ns x 50%) - 2ns] not accounting for rise/fall

times. In an SPI mode 0 or 3 implementation, the SPI master is designed to clock in data on the

next immediate rising edge of SCK after the SPI slave has clocked its data out on the preceding

falling edge. This essentially makes SPI a half-clock cycle protocol and requires extremely fast

clock-to-output times and input setup times in order to run at high clock frequencies. With

a RapidS implementation of this example, however, the full 10ns cycle time is available which

gives the slave device up to 8ns, not accounting for rise/fall times, to clock its data out. Likewise,

with RapidS, the host controller has more time available to output its data to the slave since the

slave device would be clocking that data in a full clock cycle later.

SCK

HOLD

Hold

AT25DF641A датащи(PDF) 45 Page - ATMEL Corporation