AT25DF641A datasheet(33/57 Pages) ATMEL

33 / 57 page

8693A–DFLASH–8/10

Atmel AT25DF641A [Preliminary]

10.5

Read OTP Security Register

The OTP Security Register can be sequentially read in a similar fashion to the Read Array oper-

ation up to the maximum clock frequency specified by f

MAX. To read the OTP Security Register,

the CS pin must first be asserted and the opcode of 77h must be clocked into the device. After

the opcode has been clocked in, the three address bytes must be clocked in to specify the start-

ing address location of the first byte to read within the OTP Security Register. Following the

three address bytes, two dummy bytes must be clocked into the device before data can be

output.

After the three address bytes and the dummy bytes have been clocked in, additional clock

cycles will result in OTP Security Register data being output on the SO pin. When the last byte

(00007Fh) of the OTP Security Register has been read, the device will continue reading back at

the beginning of the register (000000h). No delays will be incurred when wrapping around from

the end of the register to the beginning of the register.

Deasserting the CS pin will terminate the read operation and put the SO pin into a high-imped-

ance state. The CS pin can be deasserted at any time and does not require that a full byte of

data be read.

Figure 10-5. Read OTP Security Register

11. Status Register Commands

11.1

Read Status Register

The 2-byte Status Register can be read to determine the device’s ready/busy status, as well as

the status of many other functions such as Hardware Locking and Software Protection. The Sta-

tus Register can be read at any time, including during an internally self-timed program or erase

operation.

To read the Status Register, the CS pin must first be asserted and the opcode of 05h must be

clocked into the device. After the opcode has been clocked in, the device will begin outputting

Status Register data on the SO pin during every subsequent clock cycle. After the second byte

of the Status Register has been clocked out, the sequence will repeat itself starting again with

the first byte of the Status Register as long as the CS pin remains asserted and the clock pin is

being pulsed. The data in the Status Register is constantly being updated, so each repeating

sequence will output new data. The RDY/BSY status is available for both bytes of the Status

SCK

MSB

01110111

410 11

812

31 32

29 30

OPCODE

AAAA

AAA

A AX X X

MSB

DDDDDDD D

ADDRESS BITS A23-A0

MSB

XXXXX X

DON'T CARE

DATA BYTE 1

HIGH-IMPEDANCE

AT25DF641A датащи(PDF) 33 Page - ATMEL Corporation

AT25DF641A датащи(HTML) 33 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57

датащи скачать

ссылки URL