ADF7242BCPZ datasheet(63/108 Pages) AD

63 / 108 page

ADF7242

Rev. 0 | Page 63 of 108

SPORT INTERFACE

The SPORT interface is a high speed synchronous serial interface

suitable for interfacing to a wide variety of MCUs and DSPs,

without the use of glue logic. These include, among others, the

ADSP-21xx, SHARC, TigerSHARC and Blackfin DSPs. Figure 116

and Figure 117 show typical application diagrams using one of

the available SPORT modes. The interface uses four signals, a clock

output (TRCLK_CKO_GP3), a receive data output (DR_GP0),

a transmit data input (DT_GP1), and a framing signal output

(IRQ2_TRFS_GP2). The IRQ2 output functionality is not

available while the SPORT interface is enabled. The SPORT

interface supports GFSK/FSK and IEEE 802.15.4 receive and

transmit operations. When using GFSK/FSK mode, the polarity of

the receive/transmit clock appearing on the TRCLK_CKO_GP3

output is programmable. A detailed overview of the function of

the interface pins for each GFSK/FSK mode SPORT configuration

is listed in Table 33. The corresponding list for IEEE 802.15.4

mode is listed in Table 34. It is possible to use the SPORT

interface for transmitting IEEE 802.15.4 frames by configuring

the ADF7242 in 2 Mbps FSK mode (see Device Configuration

section) and performing the symbol chipping operation

externally.

GFSK/FSK SPORT MODE

GFSK/FSK SPORT Mode Transmit Operation

Figure 97 illustrates the operation of the SPORT interface in the

TX state. The SPORT interface is enabled by setting Register

gp_cfg, Bit gpio_config = 1 or Bit gpio_config = 4 (0x32C[7:0])

depending on the desired clock polarity. When enabled, the

data input of the transmitter is fully controlled by the SPORT

interface. The transmit clock appears when the transmit MAC

delay (tx_max_delay) has elapsed. The ADF7242 keeps transmit-

ting the serial data presented at the DT_GP1 input until the TX

state is exited by means of a command, for example, the RC_

PHY_RDY command. A timing diagram GFSK/FSK transmit

SPORT mode is provided in Figure 13.

GFSK/FSK SPORT Mode Receive Operation

The SPORT interface supports GFSK/FSK receive operation

with a number of modes to suit particular signaling require-

ments, as shown in Figure 98. For GFSK/FSK receive SPORT

operation, set Register rc_cfg, Field rc_mode = 3 (0x13E[7:0]).

This disables any packet-level processing by the packet

manager. The operating mode of the SPORT interface can be

configured through Register gp_cfg, Bit gpio_config

(0x32C[7:0]). Table 33 shows an overview of all available

configurations. The SPORT mode configurations gpio_config =

2, 3, 5, and 6 in Register gp_cfg provide synchronization with a

programmable SWD. For these modes, the synchronization

block must be configured with appropriate register writes as

outlined in the GFSK/FSK Packet Mode Reception section,

prior to issuing the RC_RX command.

When in SPORT mode, received data continues to appear on

the interface pins until the RC_RX command is reissued or the

RX state is exited by means of an appropriate SPI command.

The following SPORT operating modes can be selected.

Field gpio_config = 4

The data clock is enabled at the TRCLK_CKO_GP3 output

together with the received data at the DR_GP0 output during

the receiver MAC delay. The GFSK/FSK SWD is ignored in this

configuration. The IRQ2_TRFS_GP2 output has no function.

Figure 10 illustrates further timing details.

Field gpio_config = 5

When a preamble signal has been detected, the data clock and

data signals start to appear at the TRCLK_CKO_GP3 and

DR_GP0 output, respectively. The IRQ2_TRFS_GP2 output

goes HIGH when the sync word has been detected in the

received GFSK/FSK bit stream. Figure 11 shows more timing

details.

Field gpio_config = 6

The data clock starts to appear at the TRCLK_CKO_GP3 output

when a valid preamble and the SWD have both been detected in

the received GFSK/FSK bit stream. The first active clock edge

corresponds with the first data bit following the GFSK/FSK

SWD appearing on the DR_GP0 output. The framing signal

IRQ2_TRFS_GP2 goes high when the SWD has been detected

in the received bit sequence. The DR_GP0 output signal should

be ignored prior to the first active clock edge appearing on the

TRCLK_CKO_GP3 output. Figure 12 illustrates the applicable

timing details.

SWD and Preamble in GFSK/FSK SPORT Mode

To configure GFSK/FSK SPORT mode, set Register rc_cfg, Field

rc_mode = 3 (0x13E[7:0]). The preamble length requirements

and tolerance options described in the GFSK/FSK Packet Mode

section also apply for SPORT mode. The ADF7242 can also

support automatic detection of a SWD in SPORT mode. The

ADF7242 SWD detection algorithm as described in the

GFSK/FSK Packet Mode Reception section applies. There are a

number of clock and data gating options available. Options

include gating received data on preamble, or SWD detection.

Refer to Table 33 for further details.

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