ADF7242BCPZ datasheet(59/108 Pages) AD

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ADF7242

Rev. 0 | Page 59 of 108

Automatic Frequency Correction (AFC)

A shown in Figure 93, the ADF7242 is equipped with a fully

automatic real-time AFC function. It is used to maintain an

optimal link budget in the presence of frequency errors between

the local oscillators of the receiver and transmitter. AFC is sup-

ported in GFSK/FSK mode only.

When AFC is enabled, an internal control loop automatically

monitors the frequency error during the preamble sequence of

the packet and adjusts the synthesizer LO using an internal

proportional integral (PI) control loop. The AFC frequency

error measurement bandwidth is targeted specifically at the

packet preamble sequence (dc free). When preamble is detected,

the AFC is locked by the radio controller. AFC lock is released if

the sync word is not detected immediately after the end of

preamble. This can be due to false lock, poor quality preamble,

and/or sync word. If the qualified preamble is followed by a

qualified sync word, the AFC lock is maintained for the

duration of the packet.

Setting Register afc_cfg, Field afc_mode = 3 (0x3F7[1:0]) enables

AFC operation with automatic preamble locking, which is the

recommended setting. The frequency error readback word in

nuously updated until the AFC is locked. The frequency correction

is maintained if the ADF7242 transitions to another state (such

as TX). It is overwritten with a new frequency correction value

when the receiver next detects valid preamble, or it can be cleared

by setting Register afc_range, Field max_afc_range = 0 and

The recommended settings for the AFC control loop parameters

are Register afc_ki_kp, Field afc_ki = 9 and Register afc_ki_kp,

Field afc_kp = 9. An example of AFC performance for a

selection of data rates is given in Table 31.

The maximum AFC correction range is set by Register afc_range,

Field max_afc_range. It has a resolution of 1 kHz. This setting

helps prevent the AFC loop from attempting to acquire signals

outside the frequency range of interest. The AFC detects and

corrects frequency errors up to ±max_afc_range from the pro-

grammed channel frequency. The nominal channel frequency is set

by the frequency control word, ch_freq[23:0]. The max_afc_range

value is generally set to less than half the bandwidth of the

baseband filter.

Postdemodulator Filter

The digital post demodulator filter, shown in Figure 93,

removes excess noise from the demodulator output. Its

bandwidth is programmable with Register dm_cfg1, Field

postdemod_bw (0x38B[7:0]) and should be optimized for the

data rate used. If the bandwidth is set too narrow, performance

degrades due to intersymbol interference. If the bandwidth is

set too wide, performance degrades due to excess noise. For

optimum performance, the post demodulator filter bandwidth

should be set to 0.75 × data rate. The following formula can be used

to determine the appropriate register setting:

postdemod_bw = roundoff(17 × 10−5 × (0.75 ×

data rate[bps]) − 4 × 10−11(0.75 × data rate[bps])2)

Refer to the Device Configuration section for recommended

postdemodulator filter settings and for example data rates.

Clock and Data Recovery (CDR)

An oversampled digital clock and data recovery (CDR) PLL is

used to resynchronize the received bit stream to a local clock in all

modulation modes. The data rate of the CDR is set by Register

dr0, Field data_rate_high (0x30E[7:0]) and Register dr1, Field

data_rate_low (0x30F[7:0]).

The maximum data rate tolerance of the CDR PLL is deter-

mined by the number of bit transitions in the transmitted

packet. For example, if using GFSK/FSK with a 101010…

preamble, a maximum tolerance of ±3.0% of the data rate is

achieved.

This tolerance is reduced during the recovery of the remainder

of the packet where data transitions may not occur on regular

intervals.

However, it is possible to tolerate uncoded payload data fields

and payload data fields with long run length coding constraints

if the data rate tolerance and packet length are both con-

strained. More details of CDR operation using uncoded packet

formats are described in the AN-915 Application Note.

The CDR is designed for fast acquisition of the recovered symbols

during the preamble and typically achieves bit synchronization

within five symbol transitions of preamble.

Table 31. Example AFC Performance

Parameter

2000 kbps, fDEV = ±500 kHz

500 kbps, fDEV = ±250 kHz

Preamble Length

11 bytes

7 bytes

Frequency Error Tolerance with AFC

±165 kHz

±190 kHz

Maximum AFC Correction Range

±80 kHz

Frequency Error Tolerance Without AFC

±55 kHz

±90 kHz

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