SC2441AEVB datasheet(31/37 Pages) SEMTECH

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 2006 Semtech Corp.

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POWER MANAGEMENT

SC2441A

Applications Information

In Figure 21,

gs1 is the gate charge needed to bring the gate-to-source

voltage V

gs to the threshold Vgs_th,

gs2 is the additional gate charge required for the switch

current to reach its full-scale value I

and

gd is the charge needed to charge gate-to-drain (Miller)

capacitance when V

ds is falling.

Switching losses occur during the time interval [t

1, t3].

Defining t

r = t3-t1. tr can be approximated as

)

(

gsp

where R

gt is the total resistance from the driver supply

rail to the gate of the MOSFET. It includes the gate driver

internal impedance R

gi, external resistance Rge and the

gate resistance R

g within the MOSFET i.e.

gt = Rgi+Rge+Rg.

gsp is the Miller plateau voltage shown in Figure 21.

Similarly an approximate expression for t

f is

gsp

gs2

Only a portion of the total losses P

g = QgVccfs is dissipated

in the MOSFET package. Here Q

g is the total gate charge

specified in the datasheet. The power dissipated within

the MOSFET package is

tg =

The total power loss of the top switch is then

t = Ptc+Pts+Ptg.

If the input supply of the power converter varies over a

wide range, then it will be necessary to weigh the relative

importance of conduction and switching losses. This is

because conduction loss is inversely proportional to the

input voltage. Switching loss however increases with the

input voltage. The total power loss of MOSFET should be

calculated and compared for high-line and low-line cases.

The worst case is then used for thermal design.

Bottom Switch:

The RMS current in bottom switch can be calculated

)

)(

(

rms

The conduction loss is then

bc=IQ2,rms

ds(on),

where R

ds(on) is the channel resistance of bottom MOSFET.

If the input voltage to output voltage ratio is high (e.g.

in=12V, Vo=1.5V), the duty ratio D will be small. Since

the bottom switch conducts with duty ratio (1-D), the

corresponding conduction losses can be quite high.

Due to non-overlapping conduction between the top and

the bottom MOSFET’s, the internal body diode or the

external Schottky diode across the drain and source

terminals always conducts prior to the turn on of the

bottom MOSFET. The bottom MOSFET switches on with

only a diode voltage between its drain and source

terminals. The switching loss

)(

(

is negligible due to near zero-voltage switching.

The gate loss is estimated as

bg =

The total bottom switch loss is then

b=Pbc+Pbs+Pbg.

Once the power losses P

loss for the top (Pt) and bottom

b) MOSFET’s are known, thermal and package design

at component and system level should be done to verify

that the maximum die junction temperature (T

j,max, usually

125oC) is not exceeded under the worst-case conditions.

The equivalent thermal impedance from junction to

ambient (

ja) should satisfy

loss

max

ja depends on the die to substrate bonding, packaging

material, the thermal contact surface, thermal compound

property, the available effective heat sink area and the

air flow condition (free or forced convection). Actual

temperature measurement of the prototype should be

carried out to verify the thermal design.

Integrated Power MOSFET Drivers

There are four internal MOSFET drivers in a dual-

channel step-down converter.

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