SC2441AEVB datasheet(35/37 Pages) SEMTECH

35 / 37 page

 2006 Semtech Corp.

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POWER MANAGEMENT

SC2441A

Applications Information

Figure 25. Bode plots of the loop response.

The resulting crossover frequency is about 49.2kHz with

phase margin 90o.

If the circuit noise makes the converter jitter, a larger C

than the calculated value can be used. Effectively the

converter bandwidth is reduced to reject high frequency

noises. The final circuit should be checked for stability

under load transients at different line voltages. The load

transient also needs to be measured to ensure that the

output voltage is within the specification window.

PC Board Layout Issues

Circuit board layout is very important for the proper

operation of high frequency switching power converters.

A power ground plane is required to reduce ground

bounces. The followings are suggested for proper layout.

Power Stage

1) Separate the power ground from the signal ground. In

SC2441A the power ground PGND1 should be tied to

the source terminal of lower MOSFETs. The signal ground

AGND should be tied to the negative terminal of the

output capacitor (output return terminal).

2) Minimize the size of pulse current loop. Place the top

MOSFET, the bottom MOSFET and the input capacitors

close to each other with short and wide traces. In addition

to the aluminum energy storage capacitors, add multi-

layer ceramic (MLC) capacitors from the input to the power

ground to improve high frequency bypass.

3) Reduce high frequency voltage ringing. Widen and

shorten the drain and source traces of the MOSFETs to

reduce stray inductances. Add a small RC snubber if

necessary to reduce the high frequency ringing at the

phase node. Sometimes slowing down the gate drive

signal also helps in reducing the high frequency ringing at

the phase node.

4) Shorten the gate driver path. Integrity of the gate drive

(voltage level, leading and falling edges) is important for

circuit operation and efficiency. Short and wide gate drive

traces reduce trace inductances. Bond wire inductance

is about 2~3nH. If the length of the PCB trace from the

gate driver to the MOSFET gate is 1 inch, the trace

inductance will be about 25nH. If the gate drive current

is 2A with 10ns rise and falling times, the voltage drops

across the bond wire and the PCB trace will be 0.6V and

5V respectively. This may slow down the switching

transient of the MOSFETs. These inductances may also

ring with the gate capacitance.

5) Put the decoupling capacitor for the gate drive power

supplies (BST and VCC) close to the IC and power ground.

100

1 .10

100

73.323

17.588

20 log G vc f() C f()

()

310

100

1 .10

90.001

94.713

arg G vc f() C f

()

180

310

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