SC2441AEVB datasheet(26/37 Pages) SEMTECH

26 / 37 page

 2006 Semtech Corp.

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POWER MANAGEMENT

SC2441A

As shown in Figure 15, the CKOUT signal of the master

SC2441A is the input sync signal for the slave SC2441A.

The R

1, C1 and C2 constitute the filtering circuit stabilizing

the phase lock loop in the slave SC2441A. R2 (between

30k

Ω and 150kΩ) determines the phase shift between

the slave CKOUT and its SYNC input.

PLL Frequency Compensation

Applying synchronizing clock with step change in frequency

adjust compensation components until overshoot and

ringing at PLLF pin is minimized.

Output Inductor and Ripple Current in Step-down

Sections

Both step-down controllers in the SC2441A operate in

synchronous continuous-conduction mode (CCM)

regardless of the output load. The output inductor

selection/design is based on the output DC and transient

requirements. Both output current and voltage ripples

are reduced with larger inductors but it takes longer to

change the inductor current during load transients.

Conversely smaller inductors results in lower DC copper

losses but the AC core losses (flux swing) and the winding

AC resistance losses are higher. A compromise is to

choose the inductance such that the peak to peak

inductor ripple current is 20% to 30% of the rated output

current.

Assume that the inductor current ripple (peak-to-peak)

δ∗Ι

ο Then the inductance will be

The peak current in the inductor becomes (1+

δ/2)*Io

and the RMS current is

rms

The followings are to be considered when choosing

inductors.

a) Inductor core material: For high efficiency applications

above 350KHz, ferrite, Kool-Mu and polypermalloy

materials should be used. Low-cost powdered iron cores

can be used for cost sensitive-applications below 350KHz

but with attendant higher core losses.

Master - Slave Mode Configuration

The configuration for SC2441A master-slave mode

operation is shown in Figure 15. The master is made

free running, the master clock frequency should be within

the synchronizing range of the slave.

In the Master-Slave mode, the SS2441A can be

synchronized to an external clock signal applied to the

SYNC pin. External filtering componets (R

1, R2, C1 and C2)

on the PLLF pin are necessary for the slave SC2441A .

The PLLF pull-up resistor is not necessary for the slave

converter.

Phase shift between the master and the slave is the

phase lag measured between the sync input and the clock

output of the slave. Typical relationship between the phase

shift and the slave value of the resistor R

2 is shown in

the “Typical Characteristics”.

For the SC2441A running at slave mode, its free-runing

frequency (internal switching frequency) set with ROSC

should be programmed 20% higher than the external

synchronization frequency.

Figure 15. Master-Slave Synchronization

Applications Information

)

(

PLLF

SYNC

CKOUT

PLLF

SYNC

CKOUT

Master

SC2441A

Slave

SC2441A

VIN

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