SA9101 datasheet(17/40 Pages) SAMES

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n-bit access

Due to new signalling procedures using the five S

n bits (Sn0 ... Sn4) of every other frame

of the CRC Multiframe structure, two possibilities of access via the microprocessor are

suported:

The standard procedure allows reading/writing the S

n-bit registers without further

support. The S

n-bit information will be updated every other frame.

The advanced procedure, allows reading/writing two S

n-bit stacks each with a size

of 5 bytes. Two status bits (SR5B6 and SR5B7) provide an indication for updating

the stack information by reading/writing five bytes per multiframe from/to the

assigned stack address. To avoid loss of information, the status bits should be

monitored at time intervals less than 2ms (1,5ms recommended). With the first

access to a stack, the associated status bit will be reset.

A Transmit or Receive Multiframe Begin interrupt is supported when Alarm Interrupt

mode is enabled (CR5B6 and CR5B7).

If one makes use of the Sn bit stack in the Double frame format it is necessary that this

be done in conjunction with an externally enforced Multi-frame structure to ensure the

proper recovery of data on the far side. This is only possible in the Non-Transparent Mode

for Timelsot 0.

Organization of the stacks:

The sequentially received S

n bits (Sn0 up to Sn4) of odd numbered frames of the multiframe

structure are re-organized to bytes containing the S

n-information of the same level (Sn0

byte up to S

n4 byte).

The S

n4 byte is the first byte to be read or written via the

microprocessor interface (refer to table 3).

Alternatively, S

n bits may be processed via the system interface,if one of the transparent

modes are enabled.

Frame

Bit Slot

Microprocessor

no.

Interface

Table 3: Organisation of the S

n-Bit Stacks

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