SC202 datasheet(16/19 Pages) SEMTECH

16 / 19 page

SC202

Applications Information (continued)

The input capacitor provides a low impedance loop for

the edges of pulsed current drawn by the PMOS switch.

Low ESR/ESL X5R ceramic capacitors are recommended

for this function. To minimize stray inductance, the capaci-

tor should be placed as closely as possible to the IN and

GND pins. Table 3 lists recommended input capacitor

options from different manufacturers.

Table 3 — Recommended Input Capacitors

Manufacturer

Part Nunber

Value

(μF)

Type

Rated

Voltage

(VDC)

Dimensions

LxWxH (mm)

Case Size

Murata

GRM188R60J475K

4.7±10%

X5R

6.3

1.6x0.8x0.8

0603

Murata

GRM188R60J106K

10±10%

X5R

6.3

1.6x0.8x0.8

0603

TaiyoYuden

JMK107BJ475KA

4.7±10%

X5R

6.3

1.6x0.8x0.8

0603

TDK

C1608X5R0J475KT

4.7±10%

X5R

6.3

1.6x0.8x0.8

0603

PCB Layout Considerations

The layout diagram in Figure 3 shows a recommended

PCB top-layer for the SC202 and supporting components.

Specified layout rules must be followed since the layout is

critical for achieving the performance specified in the

Electrical Characteristics table. Poor layout can degrade

the performance of the DC-DC converter and can contrib-

ute to EMI problems, ground bounce, and resistive voltage

losses. Poor regulation and instability can also result.

The following guidelines are recommended for designing

a PCB layout:

IN should be placed as close to the IN and GND pins

as possible. This capacitor provides a low impedance

loop for the pulsed currents present at the buck

converter’s input. Use short wide traces to minimize

trace impedance. This will also minimize EMI and

input voltage ripple by localizing the high frequency

current pulses.

OUT should be connected as closely as possible to the

OUT pin.

Use a ground plane referenced to the GND pin. Use

several vias to connect to the component side ground

to further reduce noise and interference on sensitive

circuit nodes.

Route the output voltage feedback/sense trace

(connected to the SNS pin) away from the LX node

as shown in Figure 3 to minimize noise and magnetic

interference.

Minimize the resistance from the OUT and GND pins

to the load. This will reduce errors in DC regulation

due to voltage drops in the traces.

The two smaller exposed pads on this package should

not be connected to any traces. The area beneath

these two pads must be kept clear so that they do

not make electrical contact with any traces, including

ground.

CIN

CTL2

CTL0

CTL1

CTL3

(no

connection

needed)

SNS

GND

OUT

3.8mm

3.5mm

SC202

These pads should not

be electrically

connected to the PCB.

COUT

Figure 3 — Recommended PCB Layout

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