DLPC200

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DLPS014A – APRIL 2010 – REVISED MAY 2010

DDR2 SDR Memory Interface (continued)

going LOW will be referred to as the positive edge of CK. Commands (address and control signals) are

registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is

referenced to both edges of DQS as well as to both edges of CK. Read and write accesses to the DDR2 SDRAM

are burst-oriented; accesses start at a selected location and continue for a programmed number of locations in a

programmed sequence.

Accesses begin with the registration of an ACTIVATE command, which is then followed by a READ or WRITE

command. The address bits registered coincident with the ACTIVATE command are used to select the bank and

row to be accessed. The address bits registered coincident with the READ or WRITE command are used to

select the bank and the starting column location for the burst access.

DDR2 SDR MEMORY INTERFACE TIMING REQUIREMENTS

PARAMETER

MIN

MAX

UNIT

Cycle time reference

5.0

8.0

ns

2.4

4.16

ns

2.4

4.16

ns

Command setup

200

ps

Command hold

275

ps

Address setup

400

ps

Address hold

400

ps

Write data setup

1.5

ns

Write data hold

1.5

ns

Read data access time

-450

450

ps

Read data hold time

340

ps

Read data low impedance time

-900

450

ps

Read data high impedance time

450

ps

(1)

Output setup/ hold numbers already account for controller clock jitter. Only routing skew and memory setup/ hold need be considered in

system timing analysis.

(2)

Output setup/ hold numbers already account for controller clock jitter. Only routing skew and memory setup/ hold need be considered in

system timing analysis.

Copyright © 2010, Texas Instruments Incorporated

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