DLPC200 datasheet(21/41 Pages) TI

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PORTx_CLK

PORTx_D(23:),

PORTx(VSYNC,

PORTx_HSYNC,

PORTx_IVALID

n-2

n-1

PORTx_IVALID

(This diagram assumes the HSYNC

active edge is the Rising edge)

tp_clkper

tp_hsw

tp_hbp

tp_hfp

tp_vbp

tp_vsw

tp_vfp

tp_wh

tp_wl

tp_h

tp_su

1 Frame

1 Line

(This diagram assumes the VSYNC

active edge is the Rising edge)

PORTx_VSYNC

PORTx_HSYNC

PORTx_IVALID

PORTx_D(23:0)

PORTx_CLK

DLPC200

www.ti.com

DLPS014A – APRIL 2010 – REVISED MAY 2010

Figure 3. Input Port Interface

DLPC200 Master, I

2C Interface, for Extended Display Identification Data (EDID) programming

The DLCP200 controller I2C interface is used only to program the HDMI EDID. Upon plugging in an HDMI

source, the DMD resolution is compared to the HDMI output resolution programmed in the EDIDPROM. If the

two do not match, then the HDMI EDID is adjusted to match the DMD resolution.

The bidirectional I2C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be

connected to a positive supply via a pullup resistor when connected to the output stages of a device. Data

transfer may be initiated only when the bus is not busy.

I2C communication with this device is initiated by a master sending a Start condition, a high-to-low transition on

the SDA input/output while the SCL input is high. After the Start condition, the device address byte is sent, MSB

first, including the data direction bit (R/W).

After receiving the valid address byte, this device responds with an ACK, a low on the SDA input/output during

the high of the ACK-related clock pulse.

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