SPI_CLK

SPI_DATA

DLPC200

www.ti.com

DLPS014A – APRIL 2010 – REVISED MAY 2010

SPI Slave Interface (continued)

(output from slave)

The master pulls the slave select low. During each SPI clock cycle, a full duplex data transmission occurs:

•

The master sends a bit on the MOSI line; the slave reads it from that same line

•

The slave sends a bit on the MISO line; the master reads it from that same line

Transmissions involve two shift registers, one in the master and one in the slave; they are connected in a ring.

Data is shifted out with the most significant bit first, while shifting a new least significant bit into the same

register.

After that register has been shifted out, the master and slave have exchanged register values. If there is more

data to exchange, the shift registers are loaded with new data and the process repeats. Transmissions may

involve any number of clock cycles.

When there is no more data to be transmitted, the master stops toggling its clock. Transmissions consist of

packet commands/responses similar to the protocol defined for the USB interface. The SPI slave supports

variable length command and response packets and a master can initiate multiple such transmissions as

needed.

SPI INTERFACE TIMING REQUIREMENTS

PARAMETER

MIN

MAX

UNIT

Clock frequency, SPI_CLK

5

MHz

Clock period, SPI_CLK

29.994

30.006

ns

Pulse width low, SPI_CLK

10

ns

Pulse width high, SPI_CLK

10

ns

Setup Time – SPI_DIN valid before SPI_CLK rising edge

10

ns

Hold Time – SPI_DIN valid after SPI_CLK rising edge

5

ns

Figure 8. SPI Slave Timing

Parallel Flash Memory Interface

The Controller Parallel Flash Memory interface supports a high-speed NOR device with a 16 bit data bus and up

to 1GB of memory.

To perform a synchronous burst read on array or non-array, an initial address is driven onto the address bus,

and CE is asserted. WE and RST must already have been deasserted. ADV is asserted, and then deasserted to

latch the address. Alternately, ADV can remain asserted throughout the burst access, in which case the address

is latched on the next valid CLK edge while ADV is asserted. Once OE is asserted, the the first word is driven

onto DQ[15:0] on the next valid CLK edge after initial access latency delay. Subsequent data is output on valid

CLK edges following a minimum delay Tchqv.

The WAIT signal indicates data valid when the device is operating in synchronous mode (RCR.15=0). The WAIT

signal is only “deasserted” when data is valid on the bus. When the device is operating in synchronous non-array

read mode, such as read status, read ID, or read query, the WAIT signal is also “deasserted” when data is valid

on the bus. WAIT behavior during synchronous non-array reads at the end of word line works correctly only on

the first data access.

Copyright © 2010, Texas Instruments Incorporated

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