FS6370

achieve a desired input-frequency-to-output-frequency ratio without making both the reference and feedback divider values

comparatively large. Generally, very large values are undesirable as they degrade the bandwidth of the PLL, increasing phase jitter and

acquisition time.

To understand the operation of the feedback divider, refer to Figure 4. The M-counter (with a modulus always equal to M) is cascaded

with the dual-modulus pre-scaler. The A-counter controls the modulus of the pres-caler. If the value programmed into the A-counter is

A, the pre-scaler will be set to divide by N+1 for A pre-scaler outputs. Thereafter, the prescaler divides by N until the M-counter output

resets the A-counter, and the cycle begins again. Note that N=8, and A and M are binary numbers.

Figure 4: Feedback Divider

Suppose that the A-counter is programmed to zero. The modulus of the pre-scaler will always be fixed at N; and the entire modulus of

the feedback divider becomes MxN.

Next, suppose that the A-counter is programmed to a one. This causes the pre-scaler to switch to a divide-by-N+1 for its first divide

cycle and then revert to a divide-by-N. In effect, the A-counter absorbs (or "swallows") one extra clock during the entire cycle of the

feedback divider. The overall modulus is now seen to be equal to MxN+1.

This example can be extended to show that the feedback divider modulus is equal to MxN+A, where A<M.

3.1.3. Feedback Divider Programming

For proper operation of the feedback divider, the A-counter must be programmed only for values that are less than or equal to the M-

counter. Therefore, not all divider moduli below 56 are available for use. This is shown in Table 2.

Above a modulus of 56, the feedback divider can be programmed to any value up to 2047.

Table 2: Feedback Divider Modulus Under 56

A-Counter: FBKDIV[2:0]

M-Counter:

FBKDIV[10:3]

000

001

010

011

100

101

110

111

00000001

8

9

-

-

-

-

-

-

00000010

16

17

18

-

-

-

-

-

00000011

24

25

26

27

-

-

-

-

00000100

32

33

34

35

36

-

-

-

00000101

40

41

42

43

44

45

-

-

00000110

48

49

50

51

52

53

54

-

00000111

56

57

58

59

60

61

62

63

Feedback Divider Modulus

3.2 Post Divider Muxes

As shown in Figure 2, a mux in front of each post divider stage can select from any one of the three PLL frequencies or the reference

frequency. The mux selection is controlled by bits in the EEPROM or the control registers.

The input frequency on two of the four multiplexers (muxes C and D in Figure 2) can be altered without reprogramming by a logic-level

input on the SEL_CD pin.

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