FS6370 datasheet(21/28 Pages) ONSEMI

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FS6370

Table 13: AC Timing Specifications

Parameter

Symbol

Conditions/Description

Clock

(MHz)

Min.

Typ.

Max.

Units

Overall

EEPROM Write Cycle Time

Twc

VDD = 5.5 V

0.8

150

Output Frequency *

VDD = 3.6 V

0.8

100

MHz

VDD = 5.5 V

230

VCO Frequency *

fVCO

VDD = 3.6 V

170

MHz

VCO Gain *

AVCO

400

MHz/V

LFTC bit = 0

Loop Filter Time Constant *

LFTC bit = 1

μs

VO = 0.5 V to 4.5 V; CL = 15pF

2.0

Rise Time *

VO = 0.3 V to 3.0 V; CL = 15pF

2.1

VO = 4.5 V to 0.5 V; CL = 15pF

1.8

Fall Time *

VO = 3.0 V to 0.3 V; CL = 15pF

1.9

Tristate Enable Delay *

tPZL, tPZH

Tristate Disable Delay *

tPZL, tPZH

Output active from power-up, RUN mode via PD pin

100

μs

Clock Stabilization Time *

tSTB

After last register is written, register program mode

Divider Modulus

Feedback Divider

See also Error! Reference source not found.

2047

Reference Divider

255

Post Divider

See also Error! Reference source not found.

Clock Output (PLL A clock via CLK_A pin)

Duty Cycle *

Ratio of pulse width (as measured from rising edge to next falling

edge at 2.5V) to one clock period

100

On rising edges 500µs apart at 2.5V relative to an ideal clock,

CL=15pF, fXIN=14.318MHz, NF=220, NR=63, NPX=50, no other

PLLs active

100

Jitter, Long Term (

y(τ)) *

Tj(LT)

On rising edges 500µs apart at 2.5V relative to an ideal clock,

CL=15pF, =14.318MHz, NF=220, NR=63, NPX=50, all other

PLLs active (B=60MHz, C=40MHz, D=14.318MHz)

165

From rising edge to the next rising edge at 2.5V, CL=15pF,

fXIN=14.318MHz, NF=220, NR=63, NPX=50, no other PLLs

active

100

110

Jitter, Period (peak-peak)

tj(ΔP)

From rising edge to the next rising edge at 2.5V, CL=15pF,

fXIN=14.318MHz, NF=220, NR=63, NPX=50, all other PLLs

active (B=60MHz, C=40MHz, D=14.318MHz)

390

Clock Output (PLL B clock via CLK_B pin)

Duty Cycle *

Ratio of pulse width (as measured from rising edge to next falling

edge at 2.5V) to one clock period

100

On rising edges 500µs apart at 2.5V relative to an ideal clock,

CL=15pF, fXIN=14.318MHz, NF=220, NR=63, NPX=50, no other

PLLs active

100

Jitter, Long Term (

y(τ)) *

Tj(LT)

On rising edges 500µs apart at 2.5V relative to an ideal clock,

CL=15pF, =14.318MHz, NF=220, NR=63, NPX=50, all other

PLLs active (A=50MHz, C=40MHz, D=14.318MHz)

From rising edge to the next rising edge at 2.5V, CL=15pF,

fXIN=14.318MHz, NF=220, NR=63, NPX=50, no other PLLs

active

100

120

Jitter, Period (peak-peak)

tj(ΔP)

400

From rising edge to the next rising edge at 2.5V, CL=15pF,

fXIN=14.318MHz, NF=220, NR=63, NPX=50, all other PLLs

active (A=50MHz, C=40MHz, D=14.318MHz)

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