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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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SC312XDP512F0MPVR датащи(PDF) 868 Page - Freescale Semiconductor, Inc |
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SC312XDP512F0MPVR датащи(HTML) 868 Page - Freescale Semiconductor, Inc |
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868 / 1348 page  Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev. 2.21 870 Freescale Semiconductor 22.3.2.56 Port J Data Direction Register (DDRJ) Read: Anytime. Write: Anytime. This register configures each port J pin as either input or output. The CAN forces the I/O state to be an output on PJ7 (TXCAN4) and an input on pin PJ6 (RXCAN4). The IIC takes control of the I/O if enabled. In these cases the data direction bits will not change. The SCI2 forces the I/O state to be an output for each port line associated with an enabled output (TXD2). It also forces the I/O state to be an input for each port line associated with an enabled input (RXD2). In these cases the data direction bits will not change. The DDRJ bits revert to controlling the I/O direction of a pin when the associated peripheral module is disabled. 76543210 R DDRJ7 DDRJ6 DDRJ5 DDRJ4 0 DDRJ2 DDRJ1 DDRJ0 W Reset 00000000 = Unimplemented or Reserved Figure 22-58. Port J Data Direction Register (DDRJ) Table 22-52. DDRJ Field Descriptions Field Description 7–0 DDRJ[7:4] DDRJ[2:0] Data Direction Port J 0 Associated pin is configured as input. 1 Associated pin is configured as output. Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read on PTJ or PTIJ registers, when changing the DDRJ register. |
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