SC312XDP512F0MPVR datasheet(546/1348 Pages) FREESCALE

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Chapter 13 Periodic Interrupt Timer (S12PIT24B4CV1)

MC9S12XDP512 Data Sheet, Rev. 2.21

546

Freescale Semiconductor

13.3.0.2

PIT Force Load Timer Register (PITFLT)

Read: Anytime

Write: Anytime; writes to the reserved bits have no effect

13.3.0.3

PIT Channel Enable Register (PITCE)

Read: Anytime

Write: Anytime; writes to the reserved bits have no effect

76543210

00000000

PFLT3

PFLT2

PFLT1

PFLT0

Reset

00000000

= Unimplemented or Reserved

Figure 13-4. PIT Force Load Timer Register (PITFLT)

Table 13-2. PITFLT Field Descriptions

Field

Description

3:0

PFLT[3:0]

PIT Force Load Bits for Timer 3-0 — These bits have only an effect if the corresponding timer channel (PCE

set) is enabled and if the PIT module is enabled (PITE set). Writing a one into a PFLT bit loads the corresponding

16-bit timer load register into the 16-bit timer down-counter. Writing a zero has no effect. Reading these bits will

always return zero.

76543210

0000

PCE3

PCE2

PCE1

PCE0

Reset

00000000

= Unimplemented or Reserved

Figure 13-5. PIT Channel Enable Register (PITCE)

Table 13-3. PITCE Field Descriptions

Field

Description

3:0

PCE[3:0]

PIT Enable Bits for Timer Channel 3:0 — These bits enable the PIT channels 3-0. If PCE is cleared, the PIT

channel is disabled and the corresponding ﬂag bit in the PITTF register is cleared. When PCE is set, and if the

PIT module is enabled (PITE = 1) the 16-bit timer counter is loaded with the start count value and starts

down-counting.

0 The corresponding PIT channel is disabled.

1 The corresponding PIT channel is enabled.

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