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SC312XDP512F0MPVR датащи(PDF) 446 Page - Freescale Semiconductor, Inc |
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SC312XDP512F0MPVR датащи(HTML) 446 Page - Freescale Semiconductor, Inc |
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446 / 1348 page ![]() Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev. 2.21 446 Freescale Semiconductor Figure 10-24 shows the common 13-byte data structure of receive and transmit buffers for extended identifiers. The mapping of standard identifiers into the IDR registers is shown in Figure 10-25. All bits of the receive and transmit buffers are ‘x’ out of reset because of RAM-based implementation1. All reserved or unused bits of the receive and transmit buffers always read ‘x’. 1 Not applicable for receive buffers 2 Read-only for CPU 3 Read-only for CPU 1. Exception: The transmit priority registers are 0 out of reset. |
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