SC312XDP512F0MPVR datasheet(445/1348 Pages) FREESCALE

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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3)

MC9S12XDP512 Data Sheet, Rev. 2.21

Freescale Semiconductor

445

10.3.3

Programmer’s Model of Message Storage

The following section details the organization of the receive and transmit message buffers and the

associated control registers.

To simplify the programmer interface, the receive and transmit message buffers have the same outline.

Each message buffer allocates 16 bytes in the memory map containing a 13 byte data structure.

An additional transmit buffer priority register (TBPR) is deﬁned for the transmit buffers. Within the last

two bytes of this memory map, the MSCAN stores a special 16-bit time stamp, which is sampled from an

internal timer after successful transmission or reception of a message. This feature is only available for

transmit and receiver buffers, if the TIME bit is set (see Section 10.3.2.1, “MSCAN Control Register 0

(CANCTL0)”).

The time stamp register is written by the MSCAN. The CPU can only read these registers.

Table 10-23. CANIDMR4–CANIDMR7 Register Field Descriptions

Field

Description

7:0

AM[7:0]

Acceptance Mask Bits — If a particular bit in this register is cleared, this indicates that the corresponding bit in

the identiﬁer acceptance register must be the same as its identiﬁer bit before a match is detected. The message

is accepted if all such bits match. If a bit is set, it indicates that the state of the corresponding bit in the identiﬁer

acceptance register does not affect whether or not the message is accepted.

0 Match corresponding acceptance code register and identiﬁer bits

1 Ignore corresponding acceptance code register bit

Table 10-24. Message Buffer Organization

Offset

Address

Access

0x00X0

Identiﬁer Register 0

0x00X1

Identiﬁer Register 1

0x00X2

Identiﬁer Register 2

0x00X3

Identiﬁer Register 3

0x00X4

Data Segment Register 0

0x00X5

Data Segment Register 1

0x00X6

Data Segment Register 2

0x00X7

Data Segment Register 3

0x00X8

Data Segment Register 4

0x00X9

Data Segment Register 5

0x00XA

Data Segment Register 6

0x00XB

Data Segment Register 7

0x00XC

Data Length Register

0x00XD

Transmit Buffer Priority Register1

0x00XE

Time Stamp Register (High Byte)2

0x00XF

Time Stamp Register (Low Byte)3

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