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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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SC312XDP512F0MPVR датащи(PDF) 346 Page - Freescale Semiconductor, Inc |
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SC312XDP512F0MPVR датащи(HTML) 346 Page - Freescale Semiconductor, Inc |
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346 / 1348 page  Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) MC9S12XDP512 Data Sheet, Rev. 2.21 346 Freescale Semiconductor 7.3.2.28 Pulse Accumulator B Flag Register (PBFLG) Read: Anytime Write used in the flag clearing mechanism. Writing a one to the flag clears the flag. Writing a zero will not affect the current status of the bit. NOTE When TFFCA = 1, the flag cannot be cleared via the normal flag clearing mechanism (writing a one to the flag). Reference Section 7.3.2.6, “Timer System Control Register 1 (TSCR1)”. All bits reset to zero. PBFLG indicates when interrupt conditions have occurred. The flag can be cleared via the normal flag clearing mechanism (writing a one to the flag) or via the fast flag clearing mechanism (Reference TFFCA bit in Section 7.3.2.6, “Timer System Control Register 1 (TSCR1)”). 76543210 R 000000 PBOVF 0 W Reset 00000000 = Unimplemented or Reserved Figure 7-50. Pulse Accumulator B Flag Register (PBFLG) Table 7-36. PBFLG Field Descriptions Field Description 1 PBOVF Pulse Accumulator B Overflow Flag — This bit is set when the 16-bit pulse accumulator B overflows from 0xFFFF to 0x0000, or when 8-bit pulse accumulator 1 (PAC1) overflows from 0x00FF to 0x0000. When PACMX = 1, PBOVF bit can also be set if 8-bit pulse accumulator 1 (PAC1) reaches 0x00FF and an active edge follows on PT1. |
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