SC312XDP512F0MPVR datasheet(342/1348 Pages) FREESCALE

342 / 1348 page

Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2)

MC9S12XDP512 Data Sheet, Rev. 2.21

342

Freescale Semiconductor

7.3.2.24

Input Control System Control Register (ICSYS)

Read: Anytime

Write: Once in normal modes

All bits reset to zero.

76543210

SH37

SH26

SH15

SH04

TFMOD

PACMX

BUFEN

LATQ

Reset

00000000

Figure 7-46. Input Control System Register (ICSYS)

Table 7-30. ICSYS Field Descriptions

Field

Description

7:4

SHxy

Share Input action of Input Capture Channels x and y

0 Normal operation

1 The channel input ‘x’ causes the same action on the channel ‘y’. The port pin ‘x’ and the corresponding edge

detector is used to be active on the channel ‘y’.

TFMOD

Timer Flag Setting Mode — Use of the TFMOD bit in conjunction with the use of the ICOVW register allows a

timer interrupt to be generated after capturing two values in the capture and holding registers instead of

generating an interrupt for every capture.

By setting TFMOD in queue mode, when NOVWx bit is set and the corresponding capture and holding registers

are emptied, an input capture event will ﬁrst update the related input capture register with the main timer

contents. At the next event, the TCx data is transferred to the TCxH register, the TCx is updated and the CxF

interrupt ﬂag is set. In all other input capture cases the interrupt ﬂag is set by a valid external event on PTx.

0 The timer ﬂags C3F–C0F in TFLG1 are set when a valid input capture transition on the corresponding port pin

occurs.

1 If in queue mode (BUFEN = 1 and LATQ = 0), the timer ﬂags C3F–C0F in TFLG1 are set only when a latch

on the corresponding holding register occurs. If the queue mode is not engaged, the timer ﬂags C3F–C0F are

set the same way as for TFMOD = 0.

PACMX

8-Bit Pulse Accumulators Maximum Count

0 Normal operation. When the 8-bit pulse accumulator has reached the value 0x00FF, with the next active edge,

it will be incremented to 0x0000.

1 When the 8-bit pulse accumulator has reached the value 0x00FF, it will not be incremented further. The value

0x00FF indicates a count of 255 or more.

BUFFEN

IC Buffer Enable

0 Input capture and pulse accumulator holding registers are disabled.

1 Input capture and pulse accumulator holding registers are enabled. The latching mode is deﬁned by LATQ

control bit.

SC312XDP512F0MPVR датащи(PDF) 342 Page - Freescale Semiconductor, Inc

SC312XDP512F0MPVR датащи(HTML) 342 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL