68HC705SP7 datasheet(139/230 Pages) FREESCALE

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Simple Serial Interface

SIOP Signal Format

MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0

General Release Specification

Simple Serial Interface

9.3 SIOP Signal Format

The SIOP subsystem can be software configured for master or slave

operation. No external mode selection inputs are available (for instance,

no slave select pin).

9.3.1 Serial Clock (SCK)

The state of the SCK output remains a fixed logic level during idle

periods between data transfers. The edges of SCK indicate the

beginning of each output data transfer and latch any incoming data

received. The first bit of transmitted data is output from the SDO pin on

the first falling edge of SCK. The first bit of received data is accepted at

the SDI pin on the first rising edge of SCK after the first falling edge. The

transfer is terminated upon the eighth rising edge of SCK.

The idle state of the SCK is determined by the state of the CPHA bit in

the SCR. When the CPHA is clear, SCK will remain idle at a logical one

as shown in Figure 9-2. When the CPHA is set, SCK will remain idle at

a logical zero as shown in Figure 9-3. In both cases, the SDO changes

data on the falling edge of the SCK, and the SDI latches data in on the

rising edge of SCK.

The master and slave modes of operation differ only in the means of

sourcing the SCK. In master mode, SCK is driven from an internal

source within the MCU. In slave mode, SCK is driven from a source

external to the MCU. The SCK frequency is based on one of four

divisions of the oscillator clock that is selected by the SPR0 and SPR1

bits in the SCR.

Figure 9-2. SIOP Timing Diagram (CPHA = 0)

SCK

SDO

SDI

100 ns

BIT 1

BIT 2

BIT 3

BIT 4

BIT 5

BIT 6

BIT 7

BIT 8

BIT 1

BIT 2

BIT 3

BIT 4

BIT 5

BIT 6

BIT 7

BIT 8

(CPHA = 0)

(IDLE = 1)

Freescale Semiconductor, Inc.

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