LTC4280CUFD datasheet(18/28 Pages) LINER

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LTC4280

4280f

APPLICATIONS INFORMATION

of R5 resistance, the absence of a drain bypass capacitor,

a combination of bus wiring inductance and bus supply

output impedance. To prevent this second type of oscillation

avoid load capacitance below 10μF, alternately connect an

external capacitor from the MOSFET gate to ground with

a value greater than 1.5μF.

Supply Transients

The LTC4280 is designed to ride through supply transients

caused by load steps. If there is a shorted load and the

parasitic inductance back to the supply is greater than

0.5μH, there is a chance that the supply collapses before

the active current limit circuit brings down the GATE pin.

If this occurs, the undervoltage monitors pull the GATE

pin low. The undervoltage lockout circuit has a 2μs ﬁlter

time after VDD drops below 2.74V. The UV pin reacts in

2μs to shut the GATE off, but it is recommended to add a

ﬁlter capacitor CF to prevent unwanted shutdown caused

by a transient. Eventually either the UV pin or undervoltage

lockout responds to bring the current under control before

the supply completely collapses.

Supply Transient Protection

The LTC4280 is safe from damage with supply voltages up

to 24V. However, spikes above 24V may damage the part.

During a short-circuit condition, large changes in current

ﬂowing through power supply traces may cause inductive

voltage spikes which exceed 24V. To minimize such spikes,

the power trace inductance should be minimized by using

wider traces or heavier trace plating. Also, a snubber circuit

dampens inductive voltage spikes. Build a snubber by using

a 100Ω resistor in series with a 0.1μF capacitor between

VDD and GND. A surge suppressor, Z1 in Figure 1, at the

input can also prevent damage from voltage surges.

Design Example

As a design example, take the following speciﬁcations:

VIN = 12V, IMAX = 5A, IINRUSH = 1A, 5ms FILTER time,

CL=330μF,VUV(ON)=10.75V,VOV(OFF)=14.0V,VPWRGD(UP)

= 11.6V, and I2C ADDRESS = 1010011. This completed

design is shown in Figure 1.

Selection of the sense resistor, RS, is set by the overcurrent

threshold of 25mV:

MAX

0 005

The MOSFET is sized to handle the power dissipation during

inrush when output capacitor COUT is being charged. A

method to determine power dissipation during inrush is

based on the principle that:

Energy in CL = Energy in Q1

This uses:

Energy in CL ==

()( )

033

or 0.024 joules. Calculate the time it takes to charge up

COUT:

STARTUP

INRUSH

•.

•

033

The power dissipated in the MOSFET:

DISS

STARTUP

Energy in CL

TheSOA(safeoperatingarea)curvesofcandidateMOSFETs

must be evaluated to ensure that the heat capacity of the

package tolerates 6W for 4ms. The SOA curves of the

Fairchild FDC653N provide for 2A at 12V (24W) for 10ms,

satisfying this requirement. Since the FDC653N has less

than 8μF of gate capacitance and we are using a GATE

RC network, the short-circuit stability of the current limit

should be checked and improved by adding a capacitor

from GATE to SOURCE if needed.

The inrush current is set to 1A using C1:

CmF

μA

or C

GATE

INRUSH

10 33

•

.•

8nF

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