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LTC4280CUFD датащи(PDF) 17 Page - Linear Technology |
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LTC4280CUFD датащи(HTML) 17 Page - Linear Technology |
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17 / 28 page ![]() LTC4280 17 4280f APPLICATIONS INFORMATION pin or bit A3 going from high to low, if the UV pin is brought below its 0.4V reset threshold for 2μs, or if INTVCC falls below its 2.64V undervoltage lockout threshold. Finally, when EN is brought from high to low, only FAULT bits D0-D3 are cleared, and bit D4, that indicates a EN change of state, is set. Note that faults that are still present, as indicated in STATUS Register C, cannot be cleared. The FAULT register is not cleared when auto-retrying. When auto-retry is disabled the existence of a D0, D1 or D2 fault keeps the switch off. As soon as the fault is cleared, the switch turns on. If auto-retry is enabled, then a high value in C0, C1 or C2 holds the switch off and the fault register is ignored. Subsequently, when bits C0, C1 and C2 are cleared by removal of the fault condition, the switch is allowed to turn on again. The LTC4280 will set bit D2 and turn off in the event of an overcurrent fault, preventing it from remaining in an overcurrent condition. If configured to auto-retry, the LTC4280 will continually attempt to restart after cool-down cycles until it succeeds in starting up without generating an overcurrent fault. Data Converter The LTC4280 incorporates an 8-bit Δ∑ A/D converter that continuously monitors three different voltages. The Δ∑ architecture inherently averages signal noise during the measurement period. The SOURCE pin has a 1/12.5 resistive divider to monitor a full-scale voltage of 15.4V with 60mV resolution. The ADIN pin is monitored with a 1.235V full-scale and 4.82mV resolution, and the voltage between the VDD and SENSE pins is monitored with a 38.6mV full-scale and 151μV resolution. Results from each conversion are stored in registers E (Sense), F (Source) and G (ADIN), as seen in Tables 6-8, and are updated 10 times per second. Setting CONTROL register bit A5 invokes a test mode that halts the data converter so that registers E, F, and G may be written to and read from for software testing. Configuring the GPIO Pin Table 2 describes the possible states of the GPIO pin using the control register bits A6 and A7. At power-up, the default state is for the GPIO pin to go high impedance when power is good (FB pin greater than 1.235V). Other applications for the GPIO pin are to pull down when power is good, a general purpose output and a general purpose input. Current Limit Stability For many applications the LTC4280 current limit will be stable without additional components. However there are certain conditions where additional components may be needed to improve stability. The dominant pole of the current limit circuit is set by the capacitance and resistance at the gate of the external MOSFET, and larger gate capacitance makes the current limit loop more stable. Usually a total of 8nF gate to source capacitance is sufficient for stability and is typically provided by inherent MOSFET CGS, however the stability of the loop is degraded by increasing RSENSE or by reducing the size of the resistor on a gate RC network if one is used, which may require additional gate to source capacitance. Board level short- circuit testing in highly recommended as board layout can also affect transient performance, for stability testing the worst case condition for current limit stability occurs when the output is shorted to ground after a normal startup. There are two possible parasitic oscillations when the MOSFET operates as a source follower when ramping at power-up or during current limiting. The first type of oscillation occurs at high frequencies, typically above 1MHz. This high frequency oscillation is easily damped with R5 as shown in Figure 1. In some applications, one may find that R5 helps in short-circuit transient recovery as well. However, too large of an R5 value will slow down the turn-off time. The recommended R5 range is between 5Ω and 500Ω. The second type of source follower oscillation occurs at frequencies between 200kHz and 800kHz due to the load capacitance being between 0.2μF and 9μF, the presence |
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